View TMC22053AKHC_4465851.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

www.cadeka.com
TMC22x5yA
Multistandard Digital Video Decoder
Three-Line Adaptive Comb Decoder Family, 8 & 10 bit Features
* Very high performance, low cost * Adaptive comb-based decoding * Multiple pin-compatible versions - 3-line, 2-line, and band-split - 8- and 10-bit processing * Internal digital linestores * Supports NTSC/PAL field and NTSC frame based decoding * Multiple input formats - CCIR-601/624 (D1), D2, CVBS, YC * Multiple output formats - CCIR-601/624 (D1), RGB, YCBCR * 10-18 Mpps data rate * Parallel and serial control interface * Single +5V power supply
Description
The TMC22x5yA family of Digital Video Decoders offers unprecedented, broadcast-quality video processing performance in a single chip. It accepts line-locked or subcarrierlocked composite, YC, or D1 digital video and produces digital components in a variety of formats. An internal three-line adaptive comb decoder structure produces optimal picture quality with a wide range of source material. NTSC/PAL field and NTSC frame based decoding is supported with external memory. Full comb programmability allows the user to tailor the decoder's response to a particular systems goals. A family of products offers 3-line, 2-line, and simple decoders in 8-bit and 10-bit versions--all in a pin and softwarecompatible format. Serial and parallel control ports are provided. These submicron CMOS devices are packaged in a 100-lead Metric Quad Flat Pack (MQFP).
Applications
* Studio television equipment * Personal computer video input * MPEG and JPEG compression inputs
Related Products
* * * * * * * TMC22071 Genlocking Video Digitizer TMC22x9x 8 bit Digital Video Encoders TMC2081 Digital Video Mixer TMC3003 Triple 10-bit D/A Converter TMC1185 10 bit A/D converter TMC2192 10 bit video encoder TMC2072 Enhanced Genlocking Video Digitizer
Block Diagram
BUFFER MASTER1-0
VIDEOA9-0 Input Processor VIDEOB9-0 Linestore2 Linestore1
Y/C Split0 Y/C Split1 Adaptive Comb Filter
Chroma Demod
G/Y9-0 Output Processor B/Cb9-0 R/Cr9-0
Y/C Split2
Comb Fail
Burst Locked Loop
CLOCK LDV HSYNC VSYNC
Internal Sync Pulse Generator Parallel Control Global Control Serial Control
FID2-0 DREF DHSYNC DVSYNC
A1-0
R/W
CS
D 7-0
SET
RESET
SER
SA2-0
SDA
SCL
65-22x5y-01
REV. 1.0.0 2/4/03
TMC22x5yA
PRODUCT SPECIFICATION
Table of Contents
Features ......................................................................1 Applications ...............................................................1 Description .................................................................1 Block Diagram ............................................................1 Contents .....................................................................2 List of Tables and Figures ........................................3 General Description ...................................................4 Input Processor...............................................................4 Adaptive Comb Filter.....................................................4 Output Processor ............................................................5 Parallel and Serial Microprocessor Interfaces................5 Pin Assignments ........................................................5 Pin Descriptions.........................................................6 Control Register Map.................................................8 Control Register Definitions ...................................11 Decoder Introduction...............................................40 YC Separation ..............................................................40 Comb Filter Architecture for YC Separation ...............41 YC Line-Based Comb Filters.......................................42 D1 Line-Based Comb Filters .......................................42 NTSC Frame and Field Based Decoders ...............42 Composite Frame-Based Comb Filters ........................42 Composite Field-Based Comb Filters ..........................42 PAL Field Comb Decoders ......................................42 Composite PAL Field Comb Filters.............................42 The TMC22x5yA Comb Filter Architecture ............43 TMC22x5yA Functional Description.......................44 Input Processor.............................................................44 Bandsplit Filter (BSF) ..................................................44 Comb Filter Input.........................................................45 Adaptive Comb Filter...................................................47 Comb Fails................................................................49 Comb Fail Detection ....................................................49 Generation of the Comb Fail Signals .....................50 Luma Error Signals ......................................................50 Hue and Saturation Error Signals.................................50 Picture Correlation .......................................................50 Adapting the Comb Filter ............................................50 XLUT ...........................................................................51 Digital Burst Locked Loop ..........................................53 Color Kill Counter .......................................................53 PAL Color Frame Bit ...................................................55 Hue Control..................................................................55 System Monitoring of the Burst Loop Error ................55 Clamp Circuit .............................................................. 55 Pedestal Removal ........................................................ 55 Clamp Generator ......................................................... 55 Luma Notch Filter ....................................................... 56 Matrix .......................................................................... 56 Programmable U Scalar............................................... 56 Programmable V Scalar............................................... 56 Programmable Y Scalar............................................... 56 Programmable MS Scalar............................................ 56 Fixed (B-Y) and (R-Y) Scalars ................................... 56 Y Offset ....................................................................... 57 Matrix Limiters............................................................ 57 Examples of Output Matrix Operation ........................ 57 Simple Luma Color Correction ................................... 58 CBCR MSB Inversion ................................................. 58 Output Rounding ......................................................... 58 Output Formats............................................................ 58 Decimating CBCR Data............................................... 58 Multiplexed YCBCR Output (TRS Words Inserted)... 58 YC Outputs.................................................................. 58 The LDV Clock ........................................................... 58 Sync Pulse Generator ............................................. 59 Internal Field and Line Numbering Scheme ............... 59 Timing Parameters .................................................. 61 Subcarrier Programming ............................................. 61 Horizontal Timing ....................................................... 61 Horizontal and Vertical Timing Parameters................ 61 Vertical Blanking ........................................................ 62 VINDO Operation ....................................................... 65 Video Measurement................................................. 65 Pixel Grab.................................................................... 65 Composite Line Grab .................................................. 67 Parallel Microprocessor Interface ............................... 67 Serial Control Port (R-Bus)......................................... 68 Equivalent Circuits and Threshold Levels ............ 71 Absolute Maximum Ratings.................................... 72 Operating Conditions .............................................. 73 Electrical Characteristics........................................ 75 Switching Characteristics....................................... 76 System Performance Characteristics .................... 76 Programming Examples.......................................... 77 Programming Worksheet ........................................ 81 Related Products ..................................................... 82 Ordering Information ............................................... 84
2
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
List of Tables and Figures
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Figure 1. Figure 2. Figure 3. TMC22x5yA Decoder Family ................. 4 Normalized Subcarrier Frequency as a Function of Pixel Data Rates....... 45 Comb Filter Architecture ..................... 48 Simple Example of an Adaptive Comb Filter Architecture ..................... 48 Adaption Modes ................................... 51 XLUT Input Selection ........................... 52 XLUT Output Function ......................... 52 XLUT Special Function Definitions..... 52 PAL-B,G,H,I Bruch Blanking Sequence .............................. 53 PAL-M Bruch Blanking Sequence ...... 54 Blanking Level Selection ..................... 55 Adaptive Notch Threshold Control..... 55 Matrix Limiters...................................... 57 Output Format ...................................... 58 NTSC Field and Line Numbering ........ 59 PAL B,G,H,I Field and Line Numbering .................................... 59 PAL M Field and Line Numbering ....... 59 Vertical Blanking Period ...................... 60 Vertical Burst Blanking Period............ 60 Table of Line Idents, LID[4:0] .............. 60 Timing Offsets ...................................... 61 PAL VINDO operation .......................... 63 Pixel Grab Control................................ 66 Parallel Port Control............................. 67 Serial Port Addresses .......................... 69 Figure 11. Input Processor .................................... 44 Figure 12. Complementary Bandsplit Filter ......... 44 Figure 13. Bandsplit Filter, Full Frequency Response .............................................. 45 Figure 14. Bandsplit Filter, Passband Response .............................................. 45 Figure 15. Block Diagram of Comb Filter Input ... 46 Figure 16. Signal Flow Around the Adaptive Comb Filter ........................................... 47 Figure 17. Example of a Comb Fail Using a NTSC Two Line Comb Filter........................... 49 Figure 18. Generation of Upper and Lower Comb Fail Signals ........................................... 50 Figure 19. Comb Filter Selection .......................... 51 Figure 20. XLUT Input Selection ........................... 52 Figure 21. Block Diagram of Digital Burst Locked Loop ......................................... 53 Figure 22. Gaussian Low Pass Filters.................. 54 Figure 23. Gaussian LPF Passband Detail........... 54 Figure 24. Output Processor Block Diagram....... 55 Figure 25. Adaptive Notch Filters ......................... 56 Figure 26. Luminance Notch Filter ....................... 56 Figure 27. Horizontal Timing ................................. 61 Figure 28. External HSYNC and VSYNC Timing for Field 1(3, 5, or 7) ............................. 62 Figure 29. NTSC Vertical Interval.......................... 62 Figure 30. PAL-B,G,H,I,N Vertical Interval............ 62 Figure 31. PAL-M Vertical Interval ........................ 63 Figure 32. Pixel Grab Locations............................ 64 Figure 33. Relationship Between Pixel Count and Pixel Grab Value............................ 65 Figure 34. Microprocessor Parallel Port - Write Timing.......................................... 66 Figure 35. Microprocessor Parallel Port - Read Timing.......................................... 68 Figure 36. Serial Port Read/Write Timing............. 69 Figure 37. Serial Interface - Typical Byte Transfer........................... 70 Figure 38. Equivalent Digital Input Circuit ........... 71 Figure 39. Equivalent Digital Output .................... 71 Figure 40. Threshold Levels for Three-state........ 71 Figure 41. Input Timing Parameters ..................... 72 Figure 42. Functional Block Diagram of the TMC22x5yA G/Y, B/U, and R/V Output Stage...................................................... 73 Figure 43. Output Timing Parameters .................. 74
Logic Symbol.......................................... 4 Pixel Data Format ................................... 4 Fundamental Decoder Block Diagram ...................................... 40 Figure 4. Comparison of the Frequency Spectrum of NTSC and PAL Composite Video Signals .................... 40 Figure 5. Examples of Notch and Bandpass Filters..................................................... 41 Figure 6. ............................................................... 41 Figure 7. Chrominance Vector Rotation in PAL and NTSC ...................................... 42 Figure 8. Chrominance Vector Rotation Over 4 Fields in NTSC ................................... 42 Figure 9. Chrominance Vector Rotation Over 4 Fields in PAL...................................... 42 Figure 10. TMC22x5yA Line Based Comb Filter Architecture ................................ 43
REV. 1.0.0 2/4/03
3
TMC22x5yA
PRODUCT SPECIFICATION
General Description
The TMC22x5yA digital decoder can be used as a universal input to digital video processing systems by decoding digital composite video and transcoding digital component inputs into a common data format. The digital comb filter decoder implements one of sixteen comb filter architectures to produce luminance and color difference component signals which are virtually free of the cross-color and cross-luminance artifacts associated with simple bandsplit filter decoders.
comb filtering, and simple decoding. The TMC22153A 10-bit three-line comb filter can be programmed to emulate any of the other parts. All prototyping can be performed with this version to evaluate performance tradeoffs, and lowercost versions are easily substituted in production.
Input Processor
The digitized video and clocks provided to the decoder can be either locked to the line frequency or the subcarrier frequency of the digitized waveform, providing broadcast quality decoding from the NTSC square pixel rate of 12.27 MHz to the PAL four times subcarrier pixel rate of 17.73 MHz. MSB LSB VA2 VA1 VA0 VB2 VB1 VB0 G/Y2 G/Y1 G/Y0 10 bit B/CB2 B/CB1 B/CB0 R/CR2 R/CR1 R/CR0 VA2 VB2 G/Y2 B/CB2 R/CR2 N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C
Table 1. TMC22x5yA Decoder Family
TMC2215yA TMC2205yA Function 10-bit Data 8-bit Data D1 Interface Line-Locked Mode fSC-Locked Mode Genlock Mode NTSC Frame Comb 3-Line Comb 2-Line Comb Line Grab Pixel Grab 3 2 1 3 2 1
VA8 VA9 VB9 VB8 G/Y9 G/Y8 B/CB9 B/CB 8 R/CR9 R/CR8 VA9 VA8 VB9 VB8 G/Y9 G/Y8 B/CB9 B/CB 8 R/CR9 R/CR8
***
***
8 bit
NTSC/PAL Field Comb
Figure 2. Pixel Data Format
Because the cost/performance tradeoff varies among applications, the TMC22x5yA decoder has been developed as a family of six parts. They are all assembled in the same package, and fit the same footprint. The register maps are identical.
VIDEOA9-0 VIDEOB9-0 CLOCK LDV HSYNC VSYNC MASTER BUFFER D7-0 A1-0 CS R/W
65-22x5yA-02
G/Y9-0 B/CB9-0 R/CR9-0 FID2-0 AVOUT DHSYNC DVSYNC SER SET RESET SA2-0 SDA SCL
Inputs containing embedded GRS (CADEKA Video Input Processors), TRS words (D1 multiplexed component signals), and TRS-ID words (deserialized D2 signals) can be used to lock the internal horizontal and vertical state machines to the embedded information. If this information is not provided, external horizontal and vertical syncs are required for all line-locked input formats, and are optional for NTSC inputs locked to four times the subcarrier (4*Fsc). A simple sync separator is provided for digitized inputs locked to the subcarrier frequency: the internal sync separator locks to the mid point of syncs during the vertical field group, then flywheels during the active portion of the field. For this reason, the DHSYNC and DVSYNC operations are not guaranteed in subcarrier mode.
Adaptive Comb Filter
The line based adaptive comb filter in the TMC22x5yA adds or subtracts the high frequency data from three adjacent field lines to produce the average of the high frequency luminance by canceling the chrominance signals, which in flat fields of color are 180 degrees apart. Unfortunately flat fields of color are rare and, when vertical transitions in the picture occur, the output of the comb filter contains a mixture of both high frequency luminance and chrominance, at which time the comb fails. To avoid the comb filter artifacts that occur when this happens, three sets of error signals are sent to a user-programmable lookup table, allowing the output of the comb filter to be mixed with the output of an internal bandsplit decoder. To produce these comb fail error signals, the video on each of the inputs to the comb filter is passed through a simple bandsplit decoder. The low-frequency portion of the signal is
REV. 1.0.0 2/4/03
TMC22x5yA
Multistandard Digital Video Decoder
Figure 1. Logic Symbol
The devices come in 8- and 10-bit resolution versions (see Figure 2 for data alignment between 8- and 10-bit versions). Within each resolution version there are three models, offering three-line adaptive comb filtering, two-line adaptive 4
PRODUCT SPECIFICATION
TMC22x5yA
assumed to be luminance and the high frequency portion is processed as chrominance to find the magnitude and phase of the chrominance vector. These three components are then compared across the (0H & 1H) and (1H & 2H) taps of the comb filter to produce the difference in luminance, chrominance magnitude, and chrominance phase. These differences are then translated in the user-programmable lookup table to produce the "K" signal which controls the complementary mix between the output of the comb filter and the simple bandsplit decoder. That is, the "K" signals controls how much of the combed high frequency luminance signal is subtracted from the simple bandsplit chrominance for chroma combs, or added to the low frequency output of the bandsplit for luma comb filters.
Parallel and Serial Microprocessor Interfaces
The parallel microprocessor interface employs 12 pins, the serial port uses 5. A single pin, SER, selects between the two interface modes. In parallel interface mode, one address line is decoded for access to the internal control register and its pointer. Controls are reached by loading a desired address through the 8-bit D7-0 port, followed by the desired data (read or write) for that address. The control register address pointer auto-increments to address 3Fh and then remains there. A 2-line serial interface may also be used for initialization and control. The same set of registers accessed by the parallel port is available to the serial port. The device address in the serial interface is selected via pins SA2-0. The RESET pin sets all internal state machines to their initialized conditions and places the decoder in a power-down mode. All register data are maintained while in power-down mode.
Output Processor
The demodulated chrominance signal and the luminance signal are passed through a programmable output matrix, producing RGB, YUV, or YCBCR. When the clock is at 27MHz, a D1 signal can be produced on the R/V output with the embedded TRS words fixed to the external HSYNC and VSYNC timing.
Pin Assignments
100 1 81 80 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Name G/Y1 G/Y0 LDV GND VDD B/Cb9 B/Cb8 B/Cb7 B/Cb6 B/Cb5 B/Cb4 B/Cb3 B/Cb2 B/Cb1 B/Cb0 GND VDD R/Cr9 R/Cr8 R/Cr7 R/Cr6 R/Cr5 R/Cr4 R/Cr3 R/Cr2 Pin 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Name R/Cr1 R/Cr0 GND VDD DREF FID0 FID1 FID2 DHSYNC DVSYNC D0 D1 D2 GND VDD D3 D4 D5 D6 D7 GND VDD HSYNC VSYNC BUFFER Pin 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Name RESET SET SER SA0 SA1 SA2 GND SDA SCL CS R/W A0 A1 GND VDD VIDEOB0 VIDEOB1 VIDEOB2 VIDEOB3 VIDEOB4 VIDEOB5 VIDEOB6 VIDEOB7 VIDEOB8 VIDEOB9 Pin Name 76 GND 77 VIDEOA0 VIDEOA1 78 VIDEOA2 79 VIDEOA3 80 81 VIDEOA4 82 VIDEOA5 VIDEOA6 83 84 VIDEOA7 VIDEOA8 85 86 VIDEOA9 87 MASTER0 MASTER1 88 89 CLOCK GND 90 91 VDD GND 92 G/Y9 93 G/Y8 94 95 G/Y7 96 G/Y6 G/Y5 97 G/Y4 98 99 G/Y3 100 G/Y2
30 31 50
65-22x5y-03
51
REV. 1.0.0 2/4/03
5
TMC22x5yA
PRODUCT SPECIFICATION
Pin Descriptions
Pin Name Inputs VIDEOA9-0 86, 85, 84, 83, 82, 81, 80, 79, 78, 77 75, 74, 73, 72, 71, 70, 69, 68, 67, 66 49 TTL Video input A. An 8 or 10 bit data input to the input multiplexer. For 8-bit versions (TMC2205yA) the data are left-justified (VIDEOA9-2). Video input B. An 8 or 10 bit data input to the input multiplexer. For 8-bit versions (TMC2205yA) the data are left-justified (VIDEOB9-2). Vertical sync input. A vertical sync signal (active low) occurring at the start of the first vertical sync pulse in a vertical field group. A falling edge of VSYNC which is coincident with a falling edge of HSYNC indicates field 1. This signal is active only when SPGIP1-0 = 00. Horizontal sync input. A horizontal sync signal (active low) occurring at the falling edge of the video sync. This signal is active only when SPGIP1-0 = 00. Master decoder control. 00 01 10 11 BUFFER 50 TTL Adaptive comb decoder Simple bandsplit decoder Reserved Flat notched luma and simple bandsplit chroma Pin Number Value Pin Function Description
VIDEOB9-0
TTL
VSYNC
TTL
HSYNC
48
TTL
MASTER1-0
88, 87
TTL
Control register select. This signal switches between two sets of registers which control the gain or hue values in the output matrix. When BUFFER = 0, registers 17-1F are active. When BUFFER = 1, registers 27-2F take control. Master processing clock. The clock signal can either be at twice the pixel data rate in the line locked modes, or at four times the subcarrier frequency in the subcarrier mode. The interpretation of the CLOCK signal is set by the CKSEL register bit. Programmable function pin. The function specified by the SET register is active when SET is low. The decoder returns to its previous operation when SET goes high. Green or Luminance digital output. For 8-bit versions (TMC2205yA) the data are left-justified (G/Y9-2). Blue or CB digital output. For 8-bit versions (TMC2205y) the data are left-justified (B/CB 9-2). Red or CR digital output. For 8-bit versions (TMC2205yA) the data are left-justified (R/CR 9-2). Vertical sync output. The DVSYNC signal occurs once per field and lasts for 1 video line. Horizontal sync output. The DHSYNC signal occurs once per line and lasts for 64 clock periods. Data synchronization output. LDV can be an internally or externally generated clock signal. The internal LDV signal is produced when the CLOCK input is at twice the pixel data rate (PXCK); and is a pixel data rate clock phase locked to the falling edge of the HSYNC. The external LDV can be selected under software control, and must be at the CLOCK, or a sub multiple of the CLOCK, frequency.
CLOCK
89
TTL
SET
52
TTL
Outputs G/Y9-0 93, 94, 95, 96, 97, 98, 99, 100, 1, 2 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 18, 19, 20, 21, 22, 23, 24, 25, 26, 27 35 34 3 TTL
B/CB9-0
TTL
R/CR9-0
TTL
DVSYNC DHSYNC LDV
TTL TTL TTL
6
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Pin Descriptions (cont.)
Pin Name DREF Pin Number 30 Value TTL Pin Function Description Decoder reference signal. This is a dual function pin, controlled by register 24, that can function as an active video output indicator or output as a clamp pulse. When set to the active video output function, the DREF pin is HIGH during the video portion of each line and LOW during the horizontal and vertical blanking levels. When set to output a clamp pulse, the clamp pulse is controlled by register 24 and 25 allowing a user to program when a 0.5 Sec pulse is output relative to HSYNC. Field identification output. A 3 bit field ident from the DRS signal. Parallel control port data I/O. All control parameters are loaded into and read back over this 8 bit data port. Parallel control port address inputs. These pins govern whether the microprocessor interface selects a table/register address or reads/ writes table/register contents. Parallel control port chip select. When CS is high the microprocessor interface port, D7-0, is set to HIGH impedance and ignored. When CS is LOW, the microprocessor can read or write parameters over D7-0. Parallel control port read/write control. When R/W and CS are LOW, the microprocessor can write to the control registers or XLUT over D7-0. When R/W is HIGH and CS is LOW, it can read the contents of any selected XLUT address or control register over D7-0. Chip master reset. Bringing RESET LOW sets the software reset control bit, SRESET, LOW and disables the digital outputs. If HRESET is LOW the decoder outputs remain disabled after RESET goes HIGH until the SRESET bit is set high by the host. If HRESET is HIGH when RESET goes HIGH the decoder the internal state machines are enabled. Serial/parallel interface select. This pin will select between a parallel (HIGH) or serial (LOW) interface port. Serial data interface. Bi-directional serial interface to the control port. Serial interface clock. Serial Address. Three bits providing the lsbs of the serial chip ID used to identify the decoder. Power Supply. Positive power supply for digital circuits, +5V. Ground. Ground for digital circuits, 0V.
FID2-0 P Interface D7-0 A1-0
33, 32, 31 45, 44, 43, 42, 41, 38, 37, 36 63, 62
TTL TTL TTL
CS
60
TTL
R/W
61
TTL
RESET
51
TTL
SER SDA SCL SA2-0 Power Supply VDD GND
53 58 59 56, 55, 54
TTL R-Bus R-Bus TTL
5, 17, 29, 40, 47, 65, 91 4, 16, 28, 39, 46, 57, 64, 76, 90, 92
+5 V 0.0 V
REV. 1.0.0 2/4/03
7
TMC22x5yA
PRODUCT SPECIFICATION
Control Register Map
The TMC22x5yA is initialized and controlled by a set of registers which determine the operating modes. An external controller is employed to write and read the Control Registers through either the 8-bit parallel or 2-line serial interface port. The parallel port, D7-0, is governed by pins CS, R/W, and A1-0. The serial port is controlled by SDA and SCL. Reg 00 00 00 00 00 01 01 01 01 01 01 01 01 02 02 02 02 02 02 02 03 03 03 03 03 04 05 Bit 7 6 5-3 2 1-0 7 6 5 4 3 2 1 0 7 6 5-4 3 2 1 0 7-5 4 3-2 1 0 7-0 7-0 IPMUX IP8B TDEN TBLK IPCMSB ABMUX CKSEL BLLRST VIPEN LOCK BLM KILD DMODBY CINT BLFS CCEN CCOR GAUBY GAUSEL BTH PED Name Global Control SRST HRST SET DHVEN STD Software reset Hardware reset SET pin function Output H&V sync enable Selects video standard reserved, set to zero Input mux control 8 bit input format TRS detect enable TRS blank enable Chroma input msb invert AB mux control Input clock rate select BLL auto. reset enable Video Input Processor enable Global lock mode BLL lock mode Color kill disable Demod bypass CBCR interpolation enable Burst loop filter select Chroma coring enable Chroma coring threshold Gaussian filter bypass Gaussian filter select Burst threshold Pedestal Pedestal level Function
Reg 06 06 06 06 06 06 07 07 07 07 07 07 07 07
Bit 7-6 5 4 3-2 1 0 7 6 5 4 3 2 1 0
Name
Function reserved, set to zero
Luma Processor Control ANEN ANR ANT ANSEL NOTCH LS1BY LS1IN LS2DLY SPLIT BSFBY BSFSEL BSFMSB GRSDLY Adaptive notch enable Adaptive notch rounding Adaptive notch threshold Adaptive notch select Notch enable Line store 1 bypass Line store 1 input Line store 2 delay Line store 2 data width Bandsplit filter bypass Bandsplit filter select Inverts msb of bandsplit filter Delays input to GRS decode by 1H Mid-sync level Extended DRS 09 09 0A 0A 0A 0A 0A 0A 0B 0B 0B 0B 0B 0B 0C 0C 0C 0C 7-4 3-0 7 6-5 4-3 2 1 0 7 6 5 4-2 1 0 7-6 5 4 3-0 DRSEN DRSCK ADAPT YCES YCSEL COMB PCKF VSTD OP8B OPLMT MSEN OPCMSB YBAL BUREN FMT422 CDEC YUVT Clock rate Video standard Output rounded to 8 bits Output limit select Mixed sync enable Chroma output msb invert Luma color correction Output burst enable Enables CBCR output mux CBCR decimation enable Enables D1 output reserved, set to zero DRS output enable DRS data rate Adaption mode YC input error signal control luma/chroma comb filter select Comb filter architecture
Comb Processor Control
Input Processor Control
Mid-Sync Level 08 7-0 MIDS
Burst Loop Control
Output Control
Chroma Processor Control
Comb Filter Control
Burst Threshold
8
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Reg 0D 0D 0D 0D 0D 0D 0D 0E 0E 0E 0E 0F 0F 0F 0F 0F 0F 10 11 12 13 14 14 14 14 15 15 15 15 16 16 16 16
Bit 7-6 5 4 3 2 1 0 7-6 5-4 3-2 1-0 7 6-5 4 3-2 1 0 7-0 7-0 7-0 7-0 7-6 5-4 3 2-0 7 6-2 1 0 7-6 5-4 3-2 1-0
Name CEST CESG YESG CESTBY XFEN FAST YWBY XIP XSF YMUX CMUX CAT DCES IPCF YCCOMP SYNC STS7-0 STB BTV AV7-0 AV9-8 STS10-8 VINDO VDIV VDOV NFDLY SPGIP MSIP
Function Chroma error signal transform Chroma error signal gain Luma error signal gain Chroma error signal bypass XLUT filter enable Adaption speed select Luma weighting bypass XLUT input select XLUT special function Y output select C output select reserved, set to zero Adaption Threshold D1 CBCR error signal Comb filter input select YC or Composite input select Sync processor select
Reg 1A 1B 1B 1B 1B 1C 1D 1D 1D 1E 1E 1F 20 20 21 22 23 24 24 24 24 24 25 26 26 26 26 26
Bit 7-0 7-6 5-3 2 1-0 7-0 7-3 2 1-0 7-1 0 7-0 7-4 3-0 7-0 7-0 7-0 7 6 5-4 3 2-0 7-0 7-6 5 4 3 2-0
Name VG07-0 YG09-8 UG010-8 VG09-8 YOFF07-0 YOFF08 SG07-0 SYSPH06-0 VAXISO SYSPH014-7 FSC3-0 FSC11-4 FSC19-12 FSC27-20 DRFSEL PFLTBY CLPSEL1-0 VCLPEN BAND2-0 CPDLY7-0
Function V gain, 8 lsbs Y gain, 2 msbs U gain, 3 msbs reserved, set to zero V gain, 2 msbs Y offset, 8 lsbs reserved, set to zero Y offset, msb Msync gain, 2 msbs 7 lsbs of phase V axis flip 8 msbs of phase Bottom 4 bits of fSC reserved, set to zero Lower 8 bits of fSC Middle 8 bits of fSC Top 8 bits of fSC Clamp pulse enable Phase filter enable Int. clamp selection Clamp bypass Clamp offset Clamp pulse delay reserved, set to zero
Normalized Subcarrier Frequency
Clamp Control
Sync Pulse Generator Sync to sync 8 lsbs Sync to burst Burst to video Active video line 8 lsbs reserved, set to zero Active video line 2 msbs reserved, set to zero Sync to sync 3 msbs reserved, set to zero Number of lines in vertical window Action inside VINDO Action outside VINDO reserved, set to zero new field detect delay SPG input select Mixed sync separator input select
Output Format Control LDVIO OPCKS DPCEN DPC LDV clock select Output clock select DPC enable Decoder product code
Buffered register set 1 Active when BUFFER pin set HIGH 27 28 29 2A 2B 2B 2B 2B 2C 2D 7-0 7-0 7-0 7-0 7-6 5-3 2 1-0 7-0 7-3 VG19-8 YOFF17-0 SG17-0 YG17-0 UG17-0 VG17-0 YG19-8 UG110-8 Msync gain, 8 lsbs Y gain, 8 lsbs U gain, 8 lsbs V gain, 8 lsbs Y gain, 2 msbs U gain, 3 msbs reserved, set to zero V gain, 2 msbs Y offset, 8 lsbs reserved, set to zero 9
Buffered register set 0 Active when BUFFER pin set LOW 17 18 19 7-0 7-0 7-0 SG07-0 YG07-0 UG07-0 Msync gain, 8 lsbs Y gain, 8 lsbs U gain, 8 lsbs
REV. 1.0.0 2/4/03
TMC22x5yA
PRODUCT SPECIFICATION
Reg 2D 2D 2E 2E 2F 30 30 30 30 30 30 30 30 31 32 33 33 33 33 34 35 36 37 37 37 37 38 39 3A 3B 3C 3C 3C 3C 3D 3E 3F 3F 3F
Bit 2 1-0 7-1 0 7-0 7 6 5 4 3 2 1 0 7-0 7-0 7 6-4 3 2-0 7-0 7-0 7-0 7-6 5-4 3-2 1-0 7-0 7-0 7-0 7-0 7-6 5-4 3-2 1-0 7-0 7-0 7 6 5-0
Name YOFF18 SG17-0 SYSPH16-0 VAXIS1 SYSPH114-7
Function Y offset, msb Msync gain, 2 msbs 7 lsbs of phase V axis flip 8 msbs of phase set to zero
Reg 40 41 41 41 41 41 41 41 41 42 42 42 42 43 43 43 43 43 43 43 44 44 45 46 47 484A 4B 4B 4B 4CFF
Bit 7-0 7 6 5 4 3 2 1 0 7 6 5 4-0 7 6 5 4 3 2 1-0 7 6-0 7-0 7-0 7-0 7-0 7 6-5 4-0 7-0
Name DDSPH LINEST BGST VACT2 PALODD VFLY FGRAB LGRAB PGRAB FLD VBLK HBLK LID YGO YGU UBO UBU VRO VRU MONO FPERR DRS PARTID REVID
Function DDS phase, 8 msbs Pixel count reset Start of burst gate Half line flag PAL Ident Vertical count reset Field grab Line grab Pixel grab Field flag (F in D1 output) Vertical blanking (V in D1 output) Horizontal blanking (H in D1 output) Line identification Y/G overflow Y/G underflow CB/B overflow CB/B underflow CR/R overflow CR/R underflow reserved Color kill active Frequency/Phase error DRS signal Reads back xxh Revision number reserved
Status - Read Only
Video Measurement LGF LGEN LGEXT PGG PGEN PGEXT PG7-0 LG7-0 FG LG8 PG10-8 GY9-2 BU9-2 RV9-2 GY1-0 BU1-0 RV1-0 Y9-2 M9-2 U9-2 V9-2 Y1-0 M1-0 U1-0 V1-0 TEST TEST VBIT20 PEDDIS CCDEN5-0 Line grab flag Line grab enable Ext line grab enable reserved, set to zero Pixel grab gate Pixel grab enable Ext pixel grab enable Pixel grab, 8 lsbs Line grab, 8 lsbs reserved, set to zero Field grab number Msb of line grab Pixel grab, 3 msbs G/Y grab, 8 msbs B/U grab, 8 msbs R/V grab, 8 msbs reserved G/Y grab, 2 lsbs B/U grab, 2 lsbs R/V grab, 2 lsbs Luma grab, 8 msbs Msync grab, 8 msbs U grab, 8 msbs V grab, 8 msbs Luma grab, 2 lsbs Msync grab, 2 lsbs U grab, 2 lsbs V grab, 2 lsbs Test Control Must be set to zero Must be set to zero V bit control Pedestal control Closed caption control
PKILL CFSTAT XOP
Phase kill from comb fail Comb filter status XLUT output reserved
Notes: 1. Functions are listed in the order of reading and writing. 2. For each register listed above up to register 3F, all bits not specified are reserved and must be set to zero to ensure proper operation.
Vertical Blanking Control
Auto-increment stops at 3F 10
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions
Global Control Register (00)
7 SRST Reg 00 Bit 7 6 HRST Name SRST 5 4 SET Description Software reset. When LOW, resets and holds internal state machines and disables outputs. When HIGH (normal), starts and runs state machines and enables outputs. This bit is ignored while HRST is high. Hardware reset. When HRST is HIGH, SRST is forced low when RESET pin is taken LOW. State machines are reset and held. When HRST is low the RESET pin can be taken HIGH at any time. The state machines remain disabled until SRST is programmed HIGH. When HRST is high the state machines are enabled as soon as the RESET pin goes HIGH. SET pin function. These bits control the set function when the SET pin goes low. A = all outputs high-impedance B = internal state machines C = burst locked loop SET 000 001 010 011 100 101 110 111 Function Reset and hold A, B, & C. Set output to BLUE and flywheel B & C. (RGB outputs) Set output to "color" and flywheel B & C (YCBCR outputs) Hold A, lock B & C to external input Reset C only Reset B & C Set output to BLUE and lock B & C to input video (RGB output) Line and pixel grab depending on VMCR6-0 (reg 30) Toggle reset function of SET = 010. For each SET = 0 pulse the chip operation will change from normal to that of SET = 010 or visa versa. 3 2 DHVEN 1 STD 0
00
6
HRST
00
5-3
SET
The first SET pulse after a software or hardware reset, with SET = 111, causes a toggle to SET = 010. 00 00 2 1-0 DHVEN STD Output H&V sync enable. Disables DHSYNC and DVSYNC signals when HIGH. Selects video standard. Selects video standard. SET 00 01 10 11 Function NTSC reserved PAL/M All PAL standards except PAL/M
REV. 1.0.0 2/4/03
11
TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Input Processor Control (01)
7 Reserved Reg 01 01 Bit 7 6 6 IPMUX Name Reserved IPMUX 5 IP8B 4 TDEN 3 TBLK 2 IPCMSB 1 ABMUX 0 CKSEL
Description Reserved, set to zero. Input mux control. Used to select the Video Input Processor, D1, or D2 data as the VA input to the input processor. VIDEOA is selected for VA and VIDEOB is selected for VB when IPMUX is set LOW. VIDEOB is selected for VA and VIDEOA for VB when IPMUX is set HIGH. For YC inputs, the luma data must be passed through the VA input and chroma through the VB input. IPMUX should be set LOW for line locked composite inputs. 8 bit input format. Bottom two bits of inputs VIDEOA9-0 and VIDEOB9-0 are set to zero when HIGH. TRS detect enable. When HIGH, the TRS words embedded in incoming video are used to reset the horizontal and vertical state machines. When LOW the externally provided or internally generated HSYNC and VSYNC are used to reset the horizontal and vertical state machines. TRS blank enable. Blanks the TRS and AUX data words when HIGH. For line locked and D1 data, the TRS and AUX data words are set to the luma and chroma blanking levels as appropriate. For D2 (4*fSC) data, the TRS and AUX data words are set to the sync tip level. Chroma input msb invert. The msb of the chroma or CBCR data are inverted when HIGH. AB mux control. Selects the primary and secondary inputs to the decoder from the DA and DB outputs of the input processor. When ABMUX is LOW, DA is selected as the primary and DB as the secondary decoder input. Input clock rate select. Set HIGH for line locked clocks and LOW for subcarrier locked clocks. Line locked clocks should be at twice the pixel data rate, and the subcarrier clock should be at four times the subcarrier frequency.
01 01
5 4
IP8B TDEN
01
3
TBLK
01 01
2 1
IPCMSB ABMUX
01
0
CKSEL
12
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Burst Loop Control (02)
7 BLLRST Reg 02 Bit 7 6 VIPEN Name BLLRST 5 LOCK Description BLL reset enable. When LOW, the automatic BLL reset is disabled. When HIGH, the BLL will be reset if the BLL loses lock and fails to reacquire lock within 8 fields. Video Input Processor enable. Selects interface protocol for CADEKA video input devices. Active only when LOCK1-0 = 10. VIPEN Function 0 1 02 5-4 LOCK Video Input Processor Interface TMC22071 Interface 4 3 BLM 2 KILD 1 DMODBY 0 CINT
02
6
VIPEN
Global Lock mode. Sets the decoder locking mode. LOCK 00 01 10 11 Function Line Locked Mode Subcarrier Locked Mode Video Input Processor Mode D1 Mode
02
3
BLM
BLL lock mode. Sets the decoder burst locking mode. BLM 0 1 Function Frequency Lock Phase Lock
02 02 02
2 1 0
KILD DMODBY CINT
Color kill disable. Color killer is disabled when HIGH. Demod bypass. Chroma data bypasses the demodulator when HIGH. CBCR interpolation enable. Interpolation of CBCR input data from 0:2:2 to 0:4:4 is enabled when HIGH.
REV. 1.0.0 2/4/03
13
TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Chroma Processor Control (03)
7 6 BLFS Reg 03 Bit 7-5 Name BLFS 5 4 CCEN Description Burst loop filter select. BLFS fS (Mpps) 000 000 001 001 010 010 011 011 100 101 110 111 03 03 4 3-2 CCEN CCOR 13.5 15 12.27 13.5 13.5 15 14.32 17.73 17.73 13.5 12.27 14.32 Recommended Criteria PAL, Line-Locked YC PAL, Line-Locked YC NTSC, Line-Locked YC PAL, Line-Locked Composite NTSC, Line-Locked YC PAL, Line-Locked Composite NTSC, Subcarrier-Locked YC PAL, Subcarrier-Locked Composite PAL, Subcarrier-Locked YC NTSC, Line-Locked Composite NTSC, Line-Locked Composite NTSC, Subcarrier-Locked Composite 3 CCOR 2 1 GAUBY 0 GAUSEL
Chroma coring enable. Enables Chroma Coring when HIGH. Chroma coring threshold. Sets the Chroma Coring threshold. CCOR 00 01 10 11 1 lsb 2 lsb 3 lsb 4 lsb Function
03 03
1 0
GAUBY GAUSEL
Gaussian filter bypass. The chroma data bypasses the Gaussian LPF when HIGH. Gaussian LPF select. Selects the Gaussian filter response to be used on the demodulated chrominance. GAUSEL 0 1 Function Select Gaussian LPF resp. 2 Select Gaussian LPF resp. 1
See Figure 22 for filter responses.
14
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Burst Threshold (04)
7 6 5 4 BTH Reg 04 Bit 7-0 Name BTH Description Burst threshold. The 8 bit value to be compared against the demodulated U and V component data. If over 127 lines occur in a field in which the burst is below this threshold, then the color is set to chroma black for the next field. 3 2 1 0
Pedestal (05)
7 6 5 4 PED Reg 05 Bit 7-0 Name PED Description Pedestal level. An 8 bit magnitude subtracted from the luma data to remove the setup before processing by the output matrix. 3 2 1 0
Luma Processor Control (06)
7 Reserved Reg 06 06 06 Bit 7-6 5 4 Name Reserved ANEN ANR 6 5 ANEN 4 ANR 3 ANT 2 1 YSEL 0 NOTCH
Description Reserved, set to zero. Adaptive notch enable. Enables adaptive notch when HIGH. Adaptive notch rounding. Sets adaptive notch rounding point. ANR 0 1 Function Round to 10 bits Round to 8 bits
06
3-2
ANT
Adaptive notch threshold level. Sets the adaptive notch threshold. ANT 00 01 10 11 Function Magnitude difference less than 32 Magnitude difference less than 24 Magnitude difference less than 16 Magnitude difference less than 8
06
1
YSEL
Adaptive notch select. Selects adaptive notch filter response. YSEL 0 1 Function Adaptive notch response ANF1 Adaptive notch response ANF2
06
0
NOTCH
Notch enable. Adaptive notch filter ANF3 selected when HIGH and ANEN is HIGH, non-adaptive notch filter selected when HIGH and ANEN is LOW. Function may be overridden by XSF (Reg 0E, bits 5-4).
REV. 1.0.0 2/4/03
15
TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Comb Processor Control (07)
7 LS1BY Reg 07 07 Bit 7 6 6 LS1IN Name LS1BY LS1IN 5 LS2DLY 4 SPLIT 3 BSFBY 2 BSFSEL 1 BSFMSB 0 GRSDLY
Description Line store 1 bypass. Bypasses linestore 1 when HIGH. Line store 1 input. Selects the input of linestore 1: LS1IN 0 1 Primary Input Secondary Input Function
07 07
5 4
LS2DLY SPLIT
Line store 2 delay. LSTORE2 uses STS to store 1H when LOW and uses VL to store SAV to EAV (or max count) when HIGH. Line store 2 delay. Splits data through LSTORE2, 9 bits chroma and 7 bits luma when HIGH (chroma combs) and 8 bits chroma and 8 bits luma when LOW (luma comb). Bandsplit filter bypass. Bandsplit filter is bypassed when HIGH. Bandsplit filter select. Selects the bandsplit filter to be used: BSFSEL 0 1 Function Select bandsplit filter response 1 Select bandsplit filter response 2
07 07
3 2
BSFBY BSFSEL
07 07
1 0
BSFMSB GRSDLY
Inverts msb of bandsplit filter. When HIGH, inverts the msb of the input to the bandsplit filter. Delays input to GRS decode. When HIGH, delays the input to the GRS extraction circuit by 1H. Genlock only.
Mid-Sync Level (08)
7 6 5 4 MIDS Reg 08 Bit 7-0 Name MIDS Description Mid sync level. Sets the mid point of syncs for the mixed sync separator, in the subcarrier locked mode. 3 2 1 0
16
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Extended DRS (09)
7 6 PCKF Reg 09 Bit 7-4 Name PCKF Description Clock rate. PCKF 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 09 3-0 VSTD 13.50 MHz reserved reserved reserved 14.32 MHz 17.73 MHz reserved reserved 12.27 MHz 14.75 MHz 15.00 MHz reserved reserved reserved reserved reserved Function 5 4 3 2 VSTD 1 0
Video Standard. Selects the video standard. VSTD 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 NTSC-M NTSC-EIAJ reserved reserved reserved reserved reserved reserved PAL-B, G, H, I PAL-M PAL-N (Argentina, Paraguay, Uruguay) PAL-N (Jamaica) reserved reserved reserved reserved Function
REV. 1.0.0 2/4/03
17
TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Output Control (0A)
7 OP8B Reg 0A 0A Bit 7 6-5 6 OPLMT Name OP8B OPLMT 5 OPLMT Description Output rounded to 8 bits. Rounds the outputs to 8 bits when HIGH. The two lsbs are set to zero. Output limit select. Sets the output format and limiters: OPLMT 00 01 Function RGB output format limited to 4 to 1016 YCBCR output format Y limited to 4 to 1016 CBCR limited to 504 RGB output format limited to 4 to 1016 YCBCR output format Y limited to 64 to 940 CBCR limited to 448 4 MSEN 3 2 OPCMSB 1 YBAL 0 BUREN
10 11
0A
4-3
MSEN
Mixed sync enable. Sets composite sync output format: MSEN 00 01 10 11 Function No sync, & "super blacks" disabled No sync, & "super blacks" disabled Sync on G/Y output only, & "super blacks" enabled Sync on RGB outputs, & "super blacks" enabled
0A 0A 0A
2 1 0
OPCMSB YBAL BUREN
Chroma output msb invert. Inverts the msb of the CBCR or Chroma output when HIGH. Luma color correction. Setting this bit HIGH forces the chroma to zero whenever the luma equals or exceeds the luma limit. Output burst enable. When HIGH, passes the burst through on the chroma channel. Sets the burst region to zero when LOW.
Notes: 1. To enable "super blacks" and disable syncs of the output simply set MSEN[1] HIGH and the sync gain to zero.
18
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Output Control (0B)
7 FMT422 Reg 0B Bit 7 6 CDEC Name FMT422 5 YUVT Description Enables CBCR output mux. When HIGH, multiplexes the CB and CR data onto the same data bus. The chroma or multiplexed CBCR output appears on the B/CB output. The R/CR output is forced low. CBCR decimation enable. When HIGH, the CBCR data are decimated to 0:2:2 in the output processor. Enables D1 output. When HIGH, enables 4:2:2 multiplexed YCBCR onto the R/CR data output with TRS words inserted into the output data stream. The Y data are still available on the G/Y output and multiplexed CBCR is available on the B/U output. Reserved, set to zero. DRS output enable. When HIGH, enables the DRS onto the G/Y output. DRS data rate. Sets the DRS output data rate. DRSCK 0 1 Function Embeds data bytes (8 bits) at PCK clock rate Embeds data nibbles (4 bits) at PXCK clock rate 4 3 Reserved 2 1 DRSEN 0 DRSCK
0B 0B
6 5
CDEC YUVT
0B 0B 0B
4-2 1 0
Reserved DRSEN DRSCK
REV. 1.0.0 2/4/03
19
TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Comb Filter Control (0C)
7 ADAPT Reg 0C Bit 7-6 Name ADAPT 6 5 YCES 4 YCSEL Description Adaption mode. Sets the 3-line comb filter adaption mode in NTSC. ADAPT[1:0] 00 01 10 Function Adapts to best of 3 types of line based comb filters in NTSC only. Adapts to the best of two field or frame based comb filters in NTSC only. 3 line (tap) comb only. Never adapts to a 2 line (tap) filter. The higher set of comb filter error signals are sent to the XLUT. NTSC or PAL comb filter. Adapts to best of two 3 line chroma comb filters in PAL only. 3 2 COMB 1 0
11 0C 5 YCES
YC input error signal control. Error signal control for YC input, luma comb. YCES 0 1 Function LPF and HPF error signal, between (0H & 1H) or (1H & 2H) in NTSC or between (0H & 2H) in PAL,are sent to XLUT LPF error signal, between (0H & 1H) and (1H & 2H) in NTSC or between (0H & 2H) in PAL, are sent to XLUT
0C
4
YCSEL
Luma/chroma comb filter select. Selects luma or chroma comb filter. YCSEL 0 1 Chroma comb filter Luma comb filter Function
0C
3-0
COMB
Comb filter architecture. COMB 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Function YC or composite comb filter architectures PAL or NTSC 3 line comb NTSC 3 line comb (0H & 1H) NTSC 3 line comb (1H & 2H) NTSC 2 line comb (0H & 1H) NTSC (2 line) field comb NTSC or PAL field comb NTSC (2 line) frame comb NTSC frame comb D1 comb filter architectures 3 line comb 3 line comb (0H & 1H) 3 line comb (1H & 2H) 3 line comb (0H & 2H) (2 line) field comb field or 2 line (0H & 1H) comb (2 line) frame comb frame comb
20
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Comb Filter Control (0D)
7 CEST Reg 0D Bit 7-6 Name CEST 6 5 CESG 4 YESG Description Chroma error signal transform. CEST 00 01 10 11 0D 5 CESG Video Standard PAL/NTSC NTSC PAL PAL Clock Rate (MHz) 4*Fsc & 13.5MHz 12.27MHz 14.75MHz 15MHz 3 CESTBY 2 XFEN 1 FAST 0 YWBY
Chroma error signal gain. CESG 0 1 Function Normal chroma fail signal levels Double the chroma error signal levels
0D
4
YESG
Luma error signal gain. YESG 0 1 Function Normal luma fail signal levels Double the luma error signal levels
0D 0D 0D
3 2 1
CESTBY XFEN FAST
Chroma error signal bypass. When HIGH, bypasses chroma error signal. XLUT filter enable. When HIGH, enables the LPF on the XLUT output. Adaption speed select. When HIGH, the 3 line comb filter selects between comb filter architectures on a pixel by pixel basis. When LOW, the selection is filtered. Luma weighting bypass. When HIGH bypasses the luma fail weighting.
0D
0
YWBY
REV. 1.0.0 2/4/03
21
TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Comb Filter Control (0E)
7 XIP Reg 0E Bit 7-6 Name XIP 6 5 XSF Description XLUT input select. Selects the comb fail signals presented to the XLUT: XIP[1:0] 00 01 10 Input to XLUT 2 bits of phase error (X[7:6]), 3 bits of chroma (X[5:3]) and luma magnitude error (X[3:0]). 4 bits of chroma (X[7:4]) and luma magnitude error (X[3:0]). 3 bits of phase error (X[7:5]), 3 bits of chroma magnitude error (X[4:2]), and 2 bits of luma magnitude error (X[1:0]). 4 bits of phase error (X[7:4]) and chroma magnitude error (X[3:0]). 4 3 YMUX 2 1 CMUX 0
11
0E
5-4
XSF
XLUT special function. XSF 00 01 10 11 Luma Comb Simple Flat with notch Flat with notch Chroma Simple Comb Simple Comb
0E
3-2
YMUX
Y output select. Output selection of luma 4:1 mux YMUX 00 01 10 11 Comb Flat - Comb Flat Simple Output
0E
1-0
CMUX
C output select. Output selection of chroma 4:1 mux CMUX 00 01 10 11 Comb Flat - Comb Flat Simple Output
22
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Comb Filter Control (0F)
7 Reserved Reg 0F 0F Bit 7 6-5 Name Reserved CAT 6 CAT Description Reserved, set to zero. Adaption threshold. Fixes threshold at which different comb filters are selected. 0 0 1 1 0F 4 DCES 0 1 0 1 5% of max error 15% of max error 25% of max error 50% of max error 5 4 DCES 3 IPCF 2 1 YCCOMP 0 SYNC
D1 CBCR error signal. When set LOW for D1 chroma comb filters: a) In 3 line comb filter architectures, the magnitude error between the component data for that pixel selects the 3 line comb or adapts to a 2 line comb. On a "CB pixel" the error signal selected on pixel (x+4) is sent to the XLUT with the magnitude difference between "CR pixels" on the same pair of lines, but from pixel (x+3). Likewise on a "CR pixel" the error signal selected on pixel (x+5) is sent to the XLUT with the magnitude difference between "CB pixels" on the same lines but from pixel (x+4). b) In 2 line comb filters the magnitude differences between the same pair of lines is always sent to the XLUT, On a "CB pixel" the error from the preceding "CR pixel" is used and on a "CR pixel" the preceding "CB pixel" would be used. When set HIGH for D1 chroma filters: This is used for 3 line comb filter architecture that are inhibited from adapting to 2 line comb filter architectures. The input to the XLUT is the magnitude error in CR between (0H & 1H) and (1H & 2H) on "CR pixels" and the magnitude error between (0H & 1H) and (1H & 2H) on "CB pixels".
0F
3-2
IPCF
Comb filter input select. Selects primary inputs to the comb filter. IPCF 0 0 1 1 0 1 0 1 Function Flat video LPF output HPF output Reserved
0F 0F
1 0
YCCOMP SYNC
YC or Composite input select. Selects YC inputs when HIGH and composite inputs when LOW. Sync processor select. The syncs are obtained by a LPF when HIGH and by the comb filter when LOW.
Sync Pulse Generator (10)
7 STS7 Reg 10 Bit 7-0 6 STS6 Name STS7-0 5 STS5 4 STS4 Description Sync to sync 8 lsbs. Bottom 8 bits of the number of pixels between sync pulses. 3 STS3 2 STS2 1 STS1 0 STS0
REV. 1.0.0 2/4/03
23
TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Sync Pulse Generator (11)
7 6 5 4 STB Reg 11 Bit 7-0 Name STB Description Sync to burst. Controls the number of pixels from sync to burst. This signal starts the burst sample and hold. In SC mode, subtract 25 from the desired delay to generate this value. 3 2 1 0
Sync Pulse Generator (12)
7 6 5 4 BTV Reg 12 Bit 7-0 Name BTV Description Burst to video. Controls the number of pixels from STB to the start of active video. 3 2 1 0
Sync Pulse Generator (13)
7 AV7 Reg 13 Bit 7-0 6 AV6 Name AV7-0 5 AV5 4 AV4 Description Active video line 8 lsbs. Bottom 8 bits of the number of pixels during the active video line. 3 AV3 2 AV2 1 AV1 0 AV0
Sync Pulse Generator (14)
7 Reserved Reg 14 14 14 14 Bit 7-6 5-4 3 2-0 Name Reserved AV9-8 Reserved STS10-8 6 5 AV9 4 AV8 Description Reserved, set to zero. Active video line 2 msbs. Two most significant bits of AV. Reserved, set to zero. Sync to sync 3 msbs. Three most significant bits of STS. 3 Reserved 2 STS10 1 STS9 0 STS8
24
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Sync Pulse Generator (15)
7 Reserved Reg 15 15 15 Bit 7 6-2 1 Name Reserved VINDO VDIV 6 5 4 VINDO Description Reserved, set to zero. Number of lines in vertical window. The number of lines (0 to 31) after the last EQ pulse that the decoder passes through the Vertical INterval winDOw. Action inside VINDO. The vertical data inside the VINDO' is passed through a simple decoder when LOW, or is passed unprocessed on the luma channel with the chroma channel set to zero when HIGH. Action outside VINDO. The vertical data after the VINDO' and before the end of vertical blanking is blanked (YUV = 0) when LOW, or passed through the simple decoder when HIGH. 3 2 1 VDIV 0 VDOV
15
0
VDOV
Sync Pulse Generator (16)
7 Reserved Reg 16 16 Bit 7-6 5-4 Name Reserved NFDLY 6 5 NFDLY Description Reserved, set to zero. new field detect delay. NTSC frame detect delay: NFDLY 00 01 10 11 16 3-2 SPGIP pixel count = 0 pixel count = 1 pixel count = 2 pixel count = 3 Function 4 3 SPGIP 2 1 MSIP 0
SPG input select. Selects the input to the Sync Pulse Generator: SPGIP 00 01 10 11 Input External HSYNC and VSYNC Digitized sync (subcarrier mode) TRS words embedded in the D1 data stream TRS words embedded in the D2 data stream
16 16
1 0
MSIP SMO
Mixed sync separator input. Set HIGH for external VIDEOB reference or LOW for output of Low Pass Filter. State Machine Offset. Set HIGH for a 1H offset and LOW for a 0H offset.
REV. 1.0.0 2/4/03
25
TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Buffered register set 0 (17) Active when BUFFER pin set LOW.
7 SG07 Reg 17 Bit 7-0 6 SG06 Name SG07-0 5 SG05 4 SG04 Description Msync gain, 8 lsbs. Bottom 8 bits of mixed sync scalar lsb = 1/256 3 SG03 2 SG02 1 SG01 0 SG00
Buffered register set 0 (18) Active when BUFFER pin set LOW.
7 YG07 Reg 18 Bit 7-0 6 YG06 Name YG07-0 5 YG05 4 YG04 Description Y gain, 8 lsbs. Bottom 8 bits of the luma gain lsb = 1/256 3 YG03 2 YG02 1 YG01 0 YG00
Buffered register set 0 (19) Active when BUFFER pin set LOW.
7 UG07 Reg 19 Bit 7-0 6 UG06 Name UG07-0 5 UG05 4 UG04 Description U gain, 8 lsbs. Bottom 8 bits of the U gain lsb = 1/256 3 UG03 2 UG02 1 UG01 0 UG00
Buffered register set 0 (1A) Active when BUFFER pin set LOW.
7 VG07 Reg 1A Bit 7-0 6 VG06 Name VG07-0 5 VG05 4 VG04 Description V gain, 8 lsbs. Bottom 8 bits of the V gain lsb = 1/256 3 VG03 2 VG02 1 VG01 0 VG00
Buffered register set 0 (1B) Active when BUFFER pin set LOW.
7 YG09 Reg 1B 1B 1B 1B Bit 7-6 5-3 2 1-0 6 YG08 Name YG09-8 UG010-8 Reserved VG09-8 5 UG010 4 UG09 3 UG08 2 Reserved 1 VG09 0 VG08
Description Y gain, 2 msb. Top 2 bits of the Y gain. msb = 2 U gain, 3 msbs. Top 3 bits of the U gain. msb = 4 Reserved, set to zero. V gain, 2 msbs. Top 2 bits of the V gain. msb = 2
26
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Buffered register set 0 (1C) Active when BUFFER pin set LOW.
7 YOFF07 Reg 1C Bit 7-0 6 YOFF06 Name YOFF07-0 5 YOFF05 4 YOFF04 3 YOFF03 2 YOFF02 1 YOFF01 0 YOFF00
Description Y offset, 8 lsbs. Bottom 8 bits of luma or RGB offset
Buffered register set 0 (1D) Active when BUFFER pin set LOW.
7 6 5 Reserved Reg 1D 1D 1D Bit 7-3 2 1-0 Name Reserved YOFF08 SG09-8 Description Reserved, set to zero. Y offset, msb. msb of YOFF Msync gain, 2 msbs. Top 2 bits of mixed sync scalar. msb = 2 4 3 2 YOFF08 1 SG09 0 SG08
Buffered register set 0 (1E) Active when BUFFER pin set LOW.
7 SYSPH06 Reg 1E 1E Bit 7-1 0 6 SYSPH05 Name SYSPH06-0 VAXIS0 5 SYSPH04 4 SYSPH03 3 SYSPH02 2 SYSPH01 1 SYSPH00 0 VAXIS0
Description 7 lsbs of phase offset. Bottom 7 bits of the 15 bit system phase offset V axis flip. Flips the sign of the V axis when HIGH.
Buffered register set 0 (1F) Active when BUFFER pin set LOW.
7 SYSPH014 Reg 1F Bit 7-0 6 SYSPH013 Name SYSPH014-7 5 SYSPH012 4 SYSPH011 3 SYSPH010 2 SYSPH09 1 SYSPH08 0 SYSPH07
Description 8 msbs of phase offset. Top 8 bits of 15 bit system phase offset.
Normalized Subcarrier Frequency (20)
7 FSC3 Reg 20 20 Bit 7-4 3-0 6 FSC2 Name FSC3-0 Reserved 5 FSC1 4 FSC0 3 2 Reserved 1 0
Description Bottom 4 bits of fsc. Bottom 4 bits of the 28 bit subcarrier SEED Reserved, set to zero.
REV. 1.0.0 2/4/03
27
TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Normalized Subcarrier Frequency (21)
7 FSC11 Reg 21 Bit 7-0 6 FSC10 Name FSC11-4 5 FSC9 4 FSC8 3 FSC7 2 FSC6 1 FSC5 0 FSC4
Description Lower 8 bits of fsc. Lower 8 bits of the 28 bit subcarrier SEED
Normalized Subcarrier Frequency (22)
7 FSC19 Reg 22 Bit 7-0 6 FSC18 Name FSC19-12 5 FSC17 4 FSC16 3 FSC15 2 FSC14 1 FSC13 0 FSC12
Description Middle 8 bits of fsc. Middle 8 bits of the 28 bit subcarrier SEED
Normalized Subcarrier Frequency (23)
7 FSC27 Reg 23 Bit 7-0 6 FSC26 Name FSC27-20 5 FSC25 4 FSC24 3 FSC23 2 FSC22 1 FSC21 0 FSC20
Description Top 8 bits of fsc. Top 8 bits of the 28 bit subcarrier SEED
28
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Normalized Subcarrier Frequency (24)
7 CLMPEN Reg 24 Bit 7 6 PFLTEN Name DREFSEL 5 CLPSEL1-0 Description Decoder Reference Signal Select. When HIGH, enables a negative going clamp pulse on the DREF pin. The position of the clamp pulse is controlled by register 24. When LOW the DREF pin is HIGH during the active video portion of each line and LOW during the horizontal and vertical blanking intervals. Phase error filter bypass. When HIGH, no filtering is done on the phase error signals for the comb filter adapter. When LOW, the filter is enabled. Internal black level clamp selection. CLMP[1:0] 00 01 10 11 Function Clamp disabled, black level set to 240 Clamp disabled, black level set to 256 Clamp enabled, use Delayed VIDEOB input as reference Clamp enabled, use LPF as reference 4 3 CLPBY 2 1 CLPOF2-0 0
24 24
6 5-4
PFLTBY CLPSEL1-0
24 24
3 2-0
VCLPEN BAND2-0
Vertical clamp filter enable. When LOW, vertical clamp filter is disabled. When HIGH, vertical clamp filter is enabled. Clamp guard band. When an error value between two consecutive lines black level is less than the guard band, it does not effect the filtered black level. BANDS[2:0] 000 001 010 011 100 101 110 111 No guard band error value < 2 error value < 4 error value < 6 error value < 8 error value < 10 error value < 12 error value < 15 Function
Normalized Subcarrier Frequency (25)
7 6 5 4 CPDLY7-0 Reg 25 Bit 7-0 Name CPDLY7-0 Description Clamp pulse delay. Controls the number of clock cycles from hsync before the 0.5 Sec clamp pulse is output to the AVOUT pin. This option is only enabled when register 24 bit 7 is set HIGH. 3 2 1 0
REV. 1.0.0 2/4/03
29
TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Output Format Control (26)
7 Reserved Reg 26 26 26 26 Bit 7-6 5 4 3 Name Reserved LDVIO OPCKS DPCEN 6 5 LDVIO 4 OPCKS 3 DPCEN 2 1 DPC 0
Description Reserved, set to zero. LDV clock select. LDV is an output when LOW and an input when HIGH Output clock select. The output data are clocked by the CLOCK pin when LOW and by the LDV pin when HIGH. DPC enable. When HIGH on the TMC22153A, the Decoder Product Code is enabled: a value written into DPC determines the decoder product emulated by the TMC22153A. In all other versions of the decoder, DPC is read-only, and returns the code of the particular encoder version installed. Decoder product code DPC 000 001 010 011 100 101 110 111 Reserved TMC22051A TMC22052A TMC22053A Reserved TMC22151A TMC22152A TMC22153A Function
26
2-0
DPC
Read/Write in the TMC22153A only. Read-only in all other devices.
Buffered register set 1 (27) Active when BUFFER pin set HIGH.
7 SG17 Reg 27 Bit 7-0 6 SG16 Name SG17-0 5 SG15 4 SG14 3 SG13 2 SG12 1 SG11 0 SG10
Description Msync gain, 8 lsbs. Bottom 8 bits of the mixed sync scalar lsb = 1/256
Buffered register set 1 (28) Active when BUFFER pin set HIGH.
7 YG17 Reg 28 Bit 7-0 6 YG16 Name YG17-0 5 YG15 4 YG14 3 YG13 2 YG12 1 YG11 0 YG10
Description Y gain, 8 lsbs. Bottom 8 bits of the luma gain lsb = 1/256
30
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Buffered register set 1 (29) Active when BUFFER pin set HIGH.
7 UG17 Reg 29 Bit 7-0 6 UG16 Name UG17-0 5 UG15 4 UG14 3 UG13 2 UG12 1 UG11 0 UG10
Description U gain, 8 lsbs. Bottom 8 bits of the U gain lsb = 1/256
Buffered register set 1 (2A) Active when BUFFER pin set HIGH.
7 VG17 Reg 2A Bit 7-0 6 VG16 Name VG17-0 5 VG15 4 VG14 3 VG13 2 VG12 1 VG11 0 VG10
Description V gain, 8 lsbs. Bottom 8 bits of the V gain lsb = 1/256
Buffered register set 1 (2B) Active when BUFFER pin set HIGH.
7 YG19 Reg 2B 2B 2B 2B Bit 7-6 5-3 2 1-0 6 YG18 Name YG19-8 UG110-8 Reserved VG19-8 5 UG110 4 UG19 3 UG18 2 Reserved 1 VG19 0 VG18
Description Y gain, 2 msbs. Top 2 bits of the Y gain msb = 2 U gain, 3 msbs. Top 3 bits of the U gain. msb = 4 reserved, set to zero V gain, 2 msbs. Top 2 bits of the V gain msb = 2
Buffered register set 1 (2C) Active when BUFFER pin set HIGH.
7 YOFF17 Reg 2C Bit 7-0 6 YOFF16 Name YOFF17-0 5 YOFF15 4 YOFF14 3 YOFF13 2 YOFF12 1 YOFF11 0 YOFF10
Description Y offset, 8 lsbs. Bottom 8 bits of luma or RGB offset
REV. 1.0.0 2/4/03
31
TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Buffered register set 1 (2D) Active when BUFFER pin set HIGH.
7 6 5 Reserved Reg 2D 2D 2D Bit 7-3 2 1-0 Name Reserved YOFF18 SG19,8 Description Reserved, set to zero. Y offset, msb. msb of YOFF Msync gain, 2 msbs. Top 2 bits of mixed sync scalar msb = 2 4 3 2 YOFF18 1 SG19 0 SG18
Buffered register set 1 (2E) Active when BUFFER pin set HIGH.
7 SYSPH16 Reg 2E 2E Bit 7-1 0 6 SYSPH15 Name SYSPH16-0 VAXIS1 5 SYSPH14 4 SYSPH13 3 SYSPH12 2 SYSPH11 1 SYSPH10 0 VAXISO
Description 7 lsbs of phase offset. Bottom 7 bits of the 15 bit system phase offset V axis flip. Flips the sign of the V axis when HIGH.
Buffered register set 1 (2F) Active when BUFFER pin set HIGH.
7 SYSPH114 Reg 2F Bit 7-0 6 SYSPH113 Name SYSPH114-7 5 SYSPH112 4 SYSPH111 3 SYSPH110 2 SYSPH19 1 SYSPH18 0 SYSPH17
Description 8 msbs of phase offset. Top 8 bits of 15 bit system phase offset.
32
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Video Measurement (30)
7 Reserved Reg 30 30 30 Bit 7 6 5 6 LGF Name Reserved LGF LGEN 5 LGEN 4 LGEXT 3 RESERVED 2 PGG 1 PGEN 0 PGEXT
Description Reserved, set to zero. Line grab flag. Set HIGH when the decoder has grabbed a line, and must be reset LOW before another line can be grabbed. Line grab enable. When HIGH, the line grabber is used to freeze the contents of the line store, at the programmed line and field count. The phase and frequency of the frozen line are also stored from the DRS, and are continually used to reset the DDS, once per line, until LGF is set LOW. When LGEN is LOW, the line freeze is disabled, the internal loops operate normally, and the line grab signal is used only to gate the pixel grab. Ext line grab enable. The SET pin is used to produce the line grabber pulse when HIGH and the internal line decode is used when LGEXT is LOW. Reserved, set to zero. Pixel grab gate. When HIGH the pixel grab is gated by the field and line grab signals to enable one pixel per four fields in NTSC and 8 field in PAL to be grabbed. This function is disabled if PGEN is set LOW. Pixel grab enable. When HIGH the 10 bit G/Y, B/U, and R/V data, and the mixed sync and luma data after the comb filter, and the demodulated (B-Y) and (R-Y) color difference signals are grabbed once every line at the programmed pixel grab number. When LOW the contents of the pixel grab registers are held and the pixel grab pulse is ignored. Ext pixel grab enable. The SET pin is used to produce the pixel grab pulse when HIGH and the internal pixel decode is used when PGEXT is LOW.
30 30 30
4 3 2
LGEXT Reserved PGG
30
1
PGEN
30
0
PGEXT
Video Measurement (31)
7 PG7 Reg 31 Bit 7-0 6 PG6 Name PG7-0 5 PG5 4 PG4 Description Pixel grab, 8 lsbs. Bottom 8 bits of the pixel grab. 3 PG3 2 PG2 1 PG1 0 PG0
Video Measurement (32)
7 LG7 Reg 32 Bit 7-0 6 LG6 Name LG7-0 5 LG5 4 LG4 Description Line grab, 8 lsbs. Bottom 8 bits of the line grab. 3 LG3 2 LG2 1 LG1 0 LG0
REV. 1.0.0 2/4/03
33
TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Video Measurement (33)
7 Reserved Reg 33 33 33 33 Bit 7 6-4 3 2-0 Name Reserved FG LG8 PG10-8 6 5 FG Description Reserved. Field grab number. Field grab number Msb of line grab. msb of line grab Pixel grab, 3 msbs. 3 msbs of pixel grab 4 3 LG8 2 PG10 1 PG9 0 PG8
Registers 34-3C are Read-Only Register (34)
7 GY9 Reg 34 Bit 7-0 6 GY8 Name GY9-2 5 GY7 4 GY6 Description G/Y grab, 8 msbs. Top 8 bits of the "grabbed" G/Y data 3 GY5 2 GY4 1 GY3 0 GY2
Register (35)
7 BU9 Reg 35 Bit 7-0 6 BU8 Name BU9-2 5 BU7 4 BU6 Description B/U grab, 8 msbs. Top 8 bits of the "grabbed" B/U data 3 BU5 2 BU4 1 BU3 0 BU2
Register (36)
7 RV9 Reg 36 Bit 7-0 6 RV8 Name RV9-2 5 RV7 4 RV6 Description R/V grab, 8 msbs. Top 8 bits of the "grabbed" R/V data 3 RV5 2 RV4 1 RV3 0 RV2
Register (37)
7 Reserved Reg 37 37 37 37 Bit 7-6 5-4 3-2 1-0 Name Reserved GY1-0 BU1-0 RV1-0 6 5 GY1 4 GY0 Description Reserved. G/Y grab, 2 lsbs. Bottom two bits of G/Y data B/U grab, 2 lsbs. Bottom two bits of B/U data R/V grab, 2 lsbs. Bottom two bits of R/V data 3 BU1 2 BU0 1 RV1 0 RV0
34
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Register (38)
7 Y9 Reg 38 Bit 7-0 6 Y8 Name Y9-2 5 Y7 4 Y6 Description Luma grab, 8 msbs. Top 8 bits of the "grabbed" luma data after YPROC 3 Y5 2 Y4 1 Y3 0 Y2
Register (39)
7 M9 Reg 39 Bit 7-0 6 M8 Name M9-2 5 M7 4 M6 Description Msync grab, 8 msbs. Top 8 bits of the "grabbed" mixed sync data after YPROC 3 M5 2 M4 1 M3 0 M2
Register (3A)
7 U9 Reg 3A Bit 7-0 6 U8 Name U9-2 5 U7 4 U6 Description U grab, 8 msbs. Top 8 bits of the "grabbed" U data 3 U5 2 U4 1 U3 0 U2
Register (3B)
7 V9 Reg 3B Bit 7-0 6 V8 Name V9-2 5 V7 4 V6 Description V grab, 8 msbs. Top 8 bits of the "grabbed" V data 3 V5 2 V4 1 V3 0 V2
Register (3C)
7 Y1 Reg 3C 3C 3C 3C Bit 7-6 5-4 3-2 1-0 6 Y0 Name Y1-0 M1-0 U1-0 V1-0 5 M1 4 M0 Description Luma grab, 2 lsbs. Bottom 2 bits of luma data Msync grab, 2 lsbs. Bottom 2 bits of mixed sync data U grab, 2 lsbs. Bottom 2 bits of U data V grab, 2 lsbs. Bottom 2 bits of V data 3 U1 2 U0 1 V1 0 V0
REV. 1.0.0 2/4/03
35
TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Test Control (3D-3E)
7 6 5 4 TEST Reg Bit Name TEST Description Must be set to zero. Auto increment stops at 3F 3 2 1 0
3D-3E 7-0
Test Control (3F)
7 VBIT20 Reg 3F Bit 7 6 PEDDIS Name VBIT20 5 CCDEN5 4 CCDEN4 3 CCDEN3 2 CCDEN2 1 CCDEN1 0 CCDEN0
Description VBIT20 enable. When HIGH the V bit within embedded TRS words is extended through line 20 for NTSC. When LOW, this V bit is HIGH up to line 16 for NTSC. The PAL operation is unaffected by this register bit. Pedestal disable. When HIGH, pedestal is not removed from lines with LID = 00 to 06, lines 0 through 16 Closed caption data enable 5. When HIGH, enables NTSC line 21 field 0 or PAL line 22 field 0 to be passed `FLAT', through the decoder, on the luminance channel and the pedestal removal will be disabled. Closed caption data enable 4. When HIGH, enables NTSC line 22 field 0 or PAL line 23 field 0 to be passed `FLAT', through the decoder, on the luminance channel and the pedestal removal will be disabled. Closed caption data enable 3. When HIGH, enables NTSC line 23 field 0 or PAL line 24 field 0 to be passed `FLAT', through the decoder, on the luminance channel and the pedestal removal will be disabled. Closed caption data enable 2. When HIGH, enables NTSC line 283 field 1 or PAL line 334 field 1 to be passed `FLAT', through the decoder, on the luminance channel and the pedestal removal will be disabled. Closed caption data enable 1. When HIGH, enables NTSC line 284 field 1 or PAL line 335 field 1 to be passed `FLAT', through the decoder, on the luminance channel and the pedestal removal will be disabled. Closed caption data enable 0. When HIGH, enables NTSC line 285 field 1 or PAL line 336 field 1 to be passed `FLAT', through the decoder, on the luminance channel and the pedestal removal will be disabled.
3F 3F
6 5
PEDDIS CCDEN5
3F
4
CCDEN4
3F
3
CCDEN3
3F
2
CCDEN2
3F
1
CCDEN1
3F
0
CCDEN0
Status - Read Only (40)
7 6 5 4 DDSPH Reg 40 Bit 7-0 Name DDSPH Description DDS phase, 8 msbs. The top 8 bits of the sine data generated in the internal DDS. 3 2 1 0
36
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Status - Read Only (41)
7 LINEST Reg 41 41 41 41 41 41 41 41 Bit 7 6 5 4 3 2 1 0 6 BGST Name LINEST BGST VACT2 PALODD VFLY FGRAB LGRAB PGRAB 5 VACT2 4 PALODD 3 VFLY 2 FGRAB 1 LGRAB 0 PGRAB
Description Pixel count reset. Pixel count reset Start of burst gate. Start of burst gate Half line flag. Half line flag PAL Ident. PAL Ident (low on NTSC lines) Vertical count reset. Vertical count reset Field grab. Field grab Line grab. Line grab Pixel grab. Pixel grab
Status - Read Only (42)
7 FLD Reg 42 42 42 42 Bit 7 6 5 4-0 6 VBLK Name FLD VBLK HBLK LID 5 HBLK Description Field flag (F in D1 output). Field flag (F in D1 output) Vertical blanking (V in D1 output). Vertical blanking (V in D1 output) Horizontal blanking (H in D1 output). Horizontal blanking (H in D1 output) Line identification. Line identification 4 3 2 LID 1 0
Status - Read Only (43)
7 YGO Reg 43 43 43 43 43 43 43 Bit 7 6 5 4 3 2 1-0 6 YGU Name YGO YGU UBO UBU VRO VRU Reserved 5 UBO 4 UBU Description Y/G overflow. Y/G overflow Y/G underflow. Y/G underflow CB/B overflow. CB/B overflow CB/B underflow. CB/B underflow CR/R overflow. CR/R overflow CR/R underflow. CR/R underflow Reserved. 3 VRO 2 VRU 1 Reserved 0
REV. 1.0.0 2/4/03
37
TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Status - Read Only (44)
7 MONO Reg 44 44 Bit 7 6-0 Name MONO FPERR Description Color kill flag. High when burst detected and LOW when monochrome signal is detected. Frequency/Phase error. Top 7 bits of the modulo two pi frequency or phase error. Reported once per line. 6 5 4 3 FPERR 2 1 0
Status - Read Only (45)
7 6 5 4 DRS Reg 45 Bit 7-0 Name DRS Description DRS signal. The 8-bit Decoder Reference Signal. 3 2 1 0
Status - Read Only (46)
7 6 5 4 PARTID Reg 46 Bit 7-0 Name PARTID Description Part family ID. Reads back the 8-bit part ID number. Read-only. Returns CDh. 3 2 1 0
Status - Read Only (47)
7 6 5 4 REVID Reg 47 Bit 7-0 Name REVID Description Recoder revision number. REVID 05 06 10 11 TMC22x5y Revision F G A B TMC22x5yA Revision 3 2 1 0
38
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Status - Read Only (48-4A)
7 6 5 4 Reserved 3 2 1 0
Status - Read Only (4B)
7 PKILL Reg 4B 4B Bit 7 6-5 Name PKILL CFSTAT 6 CFSTAT Description Phase kill from comb fail. Phase kill from comb fail. Comb filter status. Comb filter status. CFSTAT 00 01 10 11 4B 4-0 XOP 3 tap comb 3 tap [lower] comb 3-tap [upper] comb 2 tap comb STATUS 5 4 3 2 XOP 1 0
XLUT output. XLUT output.
Status - Read Only (4C-FF)
7 6 5 4 Reserved Reg Bit Name Reserved Description Reserved. 3 2 1 0
4C-FF 7-0
REV. 1.0.0 2/4/03
39
TMC22x5yA
PRODUCT SPECIFICATION
Decoder Introduction
All composite video decoders perform fundamentally the same operation. The first stage is to separate the luminance and chrominance. The second stage is to lock the internally generated sine and cosine waveforms to the burst on the decoded chrominance signal, demodulate, and then filter the chrominance signal to produce the color difference signals. The last stage either scales the luminance and color difference signals, or converts them into red, green, and blue component video signals. These three stages are shown in Figure 3.
The complete separation of composite video signals into pure luminance (luma) and chrominance (chroma) signals is practically impossible, especially when the input source contains intraframe motion. Therefore, the luminance (luma) signal will generally contain some high frequency chrominance, termed cross luma, and the chroma signal will contains some of the high frequency luma signal, centered around the subcarrier frequency, termed cross color. The degree of cross luma and cross color is directly proportional to the filter used for the YC separation, the picture content, and the complexity of any post processing of the decoded signals.
- Y YC Filter Luminance Y Matrix
G Green -
- Composite - C Chrominance V Demodulation Burst Locked Loop sin(wt) cos(wt+) - - U
R Red -
B Blue -
65-22x5y-44
Figure 3. Fundamental Decoder Block Diagram
YC Separation
The relationship between the chrominance and luminance bandwidths is shown for both PAL and NTSC in Figure 4, wherein the shaded area denotes the part of the composite video frequency spectrum shared by both the chrominance and high frequency luminance signals.
The Luma Notch and Chroma Bandpass Technique for YC Separation
The simplest method of separating these chrominance and luminance signals, is to assume the chroma bandwidth is limited to a few hundred kilohertz around the subcarrier frequency. In this case a notch filter designed to remove just these frequencies from the composite video frequency spectrum provides the luma signal, while a bandpass filter
NTSC
PAL
Amplitude (dB) 0 -3 Luminance Chrominance Subcarrier Sound Carrier Center Frequency Amplitude (dB) 0 -3 Luminance
Chrominance Subcarrier Sound Carrier Center Frequency
Chrominance (& High Frequency Luminance)
Chrominance (& High Frequency Luminance)
-20 1 2 3 4 5 6 Frequency (MHz)
-20 1 2 3 4 4.5 Frequency (MHz)
Figure 4. Comparison of the Frequency Spectrum of NTSC and PAL Composite Video Signals
40
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Notch Filter
Amplitude (dB) 0 -3 Luminance Chrominance Subcarrier Amplitude (dB) 0 -3
Bandpass Filter
Chrominance Subcarrier
Chrominance (& High Frequency Luminance) -20 FSC Frequency -20
Chrominance (& High Frequency Luminance) FSC Frequency
Figure 5. Examples of Notch and Bandpass Filters
centered at the subcarrier frequency produces the chroma signal. This simple technique works well in pictures containing large flat areas of color, however this is rarely the case. If, as is generally true, the picture contains high frequency luma and chroma transitions, for example herring bone suit jackets, branches of trees, text, etc., cross color and cross luma artifacts are evident. The presence of cross color or cross luma is generally acceptable when viewing the decoded picture on a monitor from several feet, as would be the case in most homes on commercial television sets. However, these artifacts become increasingly difficult to process, or ignore, when the image is to be compressed or manipulated. In these cases more sophisticated methods of separating the luma and chroma signals, such as frame, field, or line based comb filter decoders, are required. Another important disadvantage of the "luma notch filter and bandpass chroma" technique is that once a notch filter has been used on the luminance channel this portion of the luminance frequency spectrum is lost. This effect becomes increasingly objectionable if the decoder component outputs are subsequently re-encoded into a composite video signal.
the V component of the chrominance signal. This document refers to line based comb decoders when discussing decoders that use inputs from sequential scan lines, i.e. lines from the same field, field based comb decoders when describing decoders that use inputs from sequential fields, and finally frame based comb decoders when examining decoders that use inputs from sequential frames.
Delay = 1/T
+
1/2
Amplitude 1.0
1/2T
1T 3/2T
2T
5/2T
3T 7/2T
4T
9/2T
5T 11/2T 6T Frequency
Figure 6. Composite Line-Based Comb Decoders
Comb Filter Architectures for YC Separation
A comb filter uses the relationship between the number of subcarrier cycles per line period, to cancel the chrominance signal over multiple line periods. This is shown for an NTSC two line comb filter in Figure 6. In NTSC there a 227.5 subcarrier cycles per line period, therefore the subcarrier can be canceled by simply adding two consecutive field scan lines. In PAL(B/I/ etc.) there are 283.7516 subcarrier cycles per line period, ignoring the 0.0016 cycle advance caused by the 25Hz offset, the PAL subcarrier can be canceled by adding the first and third line of three consecutive field scan lines. Due to the 270 degree advance, it is not possible to use information from consecutive field lines without adding a PAL modifier. A PAL modifier produces a 90 degree phase shift in the chrominance signal by multiplying the chrominance signal by a signal at two times the subcarrier frequency that is phased locked to the subcarrier burst reference in the composite video waveform. In addition the PAL modifier inverts
REV. 1.0.0 2/4/03
The phase relationship of the quadrature modulated chrominance signal can also be represented as in Figure 7. The three line comb based decoder is clearly biased towards 1H which illustrates the inherent one line delay through a 3 line comb, while a two line comb based decoder is biased towards 0H. In the following discussions a flat color represents video of constant luma and chroma magnitude and phase. In NTSC, adding two adjacent lines of flat color will cancel the chroma and leave the luma whereas subtracting two lines of flat color will cancel the luma and leave the chroma. In a 3 line comb filter the flat color on 0H and 2H is added to provide the flat color average before adding or subtracting from 1H. In PAL, adding the flat color from 0H and 2H will cancel the chroma and leave the luma while subtracting the flat color from 0H and 2H will cancel the luma and leave the chroma. However, chroma generated in this manner has no simple 41
TMC22x5yA
PRODUCT SPECIFICATION
phase relationship to the chroma on 1H. Therefore normally 0H and 2H are added together to produce the average luma across 3 lines and this is then subtracted from 1H to produce the combed chroma.
FIELD LINE no PAL U 0 1 0 1 0 1 0 1 0 N M N+1 M+1 N+2 M+2 N+3 M+3 N+4 V U 2H V Q NTSC I Q
0H and FR0H and the two consecutive field lines FR0H and FR1H are 180 degrees apart. The flat color on FR0H and FR1H can be added or subtracted to provide the luminance or chrominance to subtract from 0H.
LINE no FIELD 1 283 I 21 284 22 Q 285 23 I I Q 286 Q I 24 Q I
65-22x5y-49
(1H) Q Q (0H)
FIELD 2 I Q Q (F1H) I I (F0H) Q Q
FIELD 3 Q
FIELD 4
(FR1H) I I I I (FR0H) Q Q I I I Q I Q Q
V U U V U V
1H
0H
Q I I Q
65-22x5y-48
Figure 7. Chrominance Vector Rotation in PAL and NTSC
Figure 8. Chrominance Vector Rotation Over 4 Fields in NTSC
YC Line-Based Comb Filters
The luminance and chrominance signals, are by definition, already separated for YC inputs. However, if the original source was composite, there is a distinct possibility that there is some residual luminance (cross color) in the chrominance signal and some residual chrominance (cross luma) in the luminance signal. It is therefore legitimate to treat these signals as if they were simply the output from bandsplit filters and process the luma and chroma signals accordingly.
Composite Field-Based Comb Filters
In NTSC field based comb decoders, there is an external delay of 263 lines, therefore the 2 adjacent picture lines 0H and F0H and the two consecutive field lines F0H and F1H are 180 degrees apart. The flat color on F0H and F1H can be added or subtracted to provide the luminance or chrominance to subtract from 0H.
PAL Field Decoders
Composite, PAL Field Comb Filters
D1 Line-Based Comb Filters
A D1 data stream consists of multiplexed Y, CB and CR component data. If the original source was composite there maybe luminance (cross color) in CBCR and chrominance (cross luma) in Y. In the first case any luminance that was passed through a demodulator along with the chroma to produce the baseband CBCR color difference signals would have the same characteristics as chroma. That is to say, the cross color would advance by 180 every line in NTSC and every 2 lines in PAL. It is therefore possible to remove this cross color in a comb filter. In the latter case any chrominance that is still in the Y data can obviously be removed in a comb filter as well. The original source for the D1 signal could also have been computer graphics. In this case, the comb filter can be used to remove the picture flicker and convert the output to RGB.
In PAL field based comb decoders, there is an external delay of 312 lines, therefore the 2 adjacent picture lines 0H and F0H are 180 degrees apart. In fields 5, 6, 7, and 8 the U and V vectors are 180 degrees advanced from fields 1, 2, 3, and 4.
LINE no 23 336 V 24 (0H) 337 25 338 26 U V V U V U U V
65-22x5y-50
FIELD 1 U V U U
FIELD 2 FIELD 3 FIELD 4 V U (F0H) V V U V U (FR0H) V V U (FR0h) U V U U V
NTSC Frame and Field Based Decoders
Composite Frame-Based Comb Filters
In NTSC the chrominance vectors advance by 180 degrees every line, therefore after 525 lines the 2 adjacent frame lines
Figure 9. Chrominance Vector Rotation Over 4 Fields in PAL
42
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
The TMC22x5yA Comb Filter Architecture
The TMC22x5yA, when implementing a line based comb filter, has a core architecture as shown in Figure 10. The concept of the complementary bandsplit filter is also observed in the complementary comb filter architecture. It is therefore possible to adapt between the complementary comb filter and bandsplit filter without throwing away any of the original composite video frequency spectrum. The first step in the complementary comb filter is to separate the high frequency luminance from the chrominance signal. This combed high frequency luma signal is shown as YCOMB in Figure 10. The second step is to produce an array of comb filter error signals that indicate the degree of confidence that the YCOMB signal is just the high frequency luma and not a combination of high frequency luma and chroma smeared over the number of lines used in the comb filter. The signal representing this degree of confidence is termed "K"
in Figure 10. The last step is to provide a complementary cross fade between the YCOMB signal and the output of the complementary bandsplit filter, shown as SIMPLE in Figure 10. The FLAT signal is simply a delayed version of the input to the comb filter, therefore the sum of Output1 and Output2 will always be equal to the FLAT video input. The TMC22x53A comb filter architecture has three taps. These taps are three consecutive field lines in a line based comb, three consecutive picture lines in a field based comb, or lines that are one frame and one field line apart in the frame based comb. In addition to these different inputs to the comb filter, NTSC and PAL video signals comb over different taps in different architectures, as described in the comb filter introduction. The total internal pipeline latency is 1H + 40 pixels for 3 line comb filters, for all other comb filter and simple decoder architectures the pipeline latency is 40 pixels.
XLUT SIMPLE 1H Bandsplit Filters 1H COMB Filter YCOMB
-
Output1
Input
X
+
Simple +/- {k * Ycomb}
Output2
XLUT
K
Figure 10. TMC22x5yA Line Based Comb Filter Architecture
REV. 1.0.0 2/4/03
43
TMC22x5yA
PRODUCT SPECIFICATION
TMC22x5yA Functional Description
Input Processor
The input processor selects between the two external video sources on VIDEO A and VIDEO B. If the TRS stripper or GRS stacker is active, then the user must select the input with either the GRS (in genlock mode) or with the embedded TRS words as output VA. If the input data are separate luma and chroma or Y and CBCR data the input processor must be programmed to put the chrominance or CBCR onto output VB and the luminance or Y onto VA. To ensure that the chrominance data or the CBCR data are in two's complement arithmetic format, the register bit MSBI inverts the msb of the DB input. For composite inputs, the IPCMSB register bit should be set LOW, as the ABMUX register bit is used to select the input(s) to the comb filter.
Input LPF LPF Output
-
HPF Output
65-22x5y-53
Figure 12. Complementary Bandsplit Filter
Bandsplit Filter (BSF)
In its simple mode of operation, the TMC22x5yA uses a complementary bandsplit filter, instead of a notch filter for the luma and a bandpass for the chroma. The notch and bandpass filter technique, removes frequency bands from the composite video spectrum which can never be retrieved. The complementary bandsplit filter technique, shown in Figure 12, allows the decoded component video signals to be re-encoded into a composite video signal with the minimum of losses to the composite video spectrum.
The complementary bandsplit filter separates the base band composite video into two bands by passing it through a low pass filter and subtracting the low pass (luma) data from the composite video to produce the high pass (chroma) data. As the base bandwidths and subcarrier frequencies of the different NTSC and PAL video formats are so different, and the decoder has to be capable of working over a large frequency range, it is necessary to provide two low pass filters. These filters are selectable by the BSFSEL register bit and are independent of the video standard. A comparison of the different data rates to normalized subcarrier frequencies is provided in Table 2. The complementary bandsplit low pass frequency response is shown in Figure 13 and Figure 14.
msb x
Input Processor Control Register IPMUX IP8B TDEN TBLK
lsb ICPMSB ABMUX CKSEL
VideoA
VA
TRS Stripper (D1/D2/D3) and GRS Stacker (TMC22071)
DA
Primary Data to Comb Filter 2:2 MUX
2:2 MUX
VideoB
VB
MSB Invert
DB
Secondary Data to Comb Filter
65-22x5y-52
Figure 11. Input Processor
44
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
0 -10 -20 -30 -40 -50 -60 0.00 0.10 0.20 0.30 0.40 -70 Bandsplit Filter 1
65-22x5y-54
1 0
Bandsplit Filter 2
Attenuation (dB)
Attenuation (dB)
-1 Bandsplit Filter 2 -2 -3 -4 -5 0.00 0.05 0.10 -6 Bandsplit Filter 1
65-22x5y-55
0.50
Normalized Frequency
Normalized Frequency
Figure 13. Bandsplit Filter, Full Frequency Response
Figure 14. Bandsplit Filter, Passband Response
Table 2. Normalized Subcarrier Frequency as a Function of Pixel Data Rates
Pixel Rate (MHz) 12.27 13.50 13.50 14.32 14.75 15.00 17.73 13.5 13.5 14.30
FSC (MHz) 3.57954545 3.57954545 4.43361875 3.57954545 4.43361875 4.43361875 4.43361875 3.57561149 3.58205625 3.57561149
Normalized FSC 0.2917 0.2652 0.3284 0.2500 0.3006 0.2956 0.2500 0.2649 0.2653 0.2500 NTSC D1 pixel rate PAL-I D1 pixel rate
Comments NTSC square pixel rate
NTSC four times subcarrier (D2/D3) PAL-I square pixel rate PAL-I square pixel rate PAL-I four times subcarrier (D2/D3) PAL-M D1 pixel rate PAL-N D1 pixel rate PAL-M four times subcarrier (D2/D3) luma and chroma SIMPLE signals, and in the generation of the comb fail signals. These signals are denoted xHL, xHH, and xHF where L denotes the low frequency portion of the signal, H the high frequency portion of the signal and F the full frequency spectrum of the input signal from line x; and are shown in Figure 15.
Comb Filter Input
The inputs to the comb filter are selected from either the high frequency outputs of the bandsplit filters, if using a chroma comb filter, or the full composite waveforms when implementing a luma comb. The two sets of high and low frequency signals from the bandsplit filters are used for both the
REV. 1.0.0 2/4/03
0.15
45
TMC22x5yA
PRODUCT SPECIFICATION
0HF Primary Input 0HL
LPF
BSFSEL
-
0HH
2:1 MUX Secondary Input LS1IN
LSTORE1 [9:0] 2:1 MUX LPF
1HF 1HL
BSFSEL LS1BY
-
LSTORE2 2HH
1HH
1HH
2HH
+
1HH (lsbs) 1HL (lsbs) 2:1 MUX LSTORE2 2HX
2:1 MUX
2HF
1HL Split
LSTORE2 2HL
2HL
DELAY
VIDEOB
65-22x5y-56
Figure 15. Block Diagram of Comb Filter Input
The primary and secondary inputs are selected within the input processor. The primary input is normally the undelayed composite video signal in line, field, and frame based comb filters or either the luma or chroma channel when processing YC or D1 signals. The secondary provides the field or frame delayed composite input for field and frame based comb filters and the chroma or luma channel when processing YC or D1 signals. When implementing a line based comb filter the outputs of 1H bandsplit filter, ie 1HH, 1HL, are delayed through the second line store, LSTORE2. The number of bits delayed is dependent upon the type of comb filter being implemented. For chroma comb filters all the bits of the 1HH signal are delayed, as this information supplies the outer tap of the chroma comb filter, while only the upper bits of 1HL are delayed as this data is used only in the generation of the 46
luma error signals. In the case of luma combs an equal number of bits of the 1HH and 1HL signals are delayed and summed together to produce the 2HF signal for the outer tap of the luma comb filter. The configuration of LSTORE2 is determined by the SPLIT register bit. It is important to note that when implementing a field or frame based comb filter the secondary input must be selected by setting the LSIN register bit HIGH, and the first line store, LSTORE1, must be bypassed by setting the LS1BY register bit HIGH. For YC and D1 processing the secondary input bypasses the comb filter completely and provides the VIDEOB signal input the 3:1 multiplexer used to select the FLAT signal, see Figure 16.
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Adaptive Comb Filter
The IPCF[1:0] register bits select the inputs to the adaptive comb filter, this would normally be xHH for chroma combs, xHF for luma combs, and xHL if the luminance signal was to be sampled dropped on the output of the TMC22x5yA. The Gaussian filters in the sample drop mode already limit the chrominance bandwidth to 1.3MHz allowing a [2:1:1] data format on the output, with the luminance signal having been vertically filtered by a fixed 3 line comb filter. The SIMP selection bit is an internally generated signal based upon the comb filter selected. If a 3 line chroma, luma, or D1 comb filter is selected, due to the internal 1H delay inherent with this type of comb filter, the 1HL and 1HH signals are selected for the respective luma and chroma SIMPLE data signals. When any other type of comb filter is selected 0HL and 0HH are selected. The DLYF selection bit is also internally generated from the type of comb filter selected and whether or not the input is in either the YC or Y & CbCr (ie D1 input) data formats. The
VIDEOB data is always selected when the YCCOMP register bit is HIGH, ie for YC inputs. The selection of 1HF or 0HF depends upon the SIMP selection bit only when the YCCOMP register bit is LOW. Therefore, when YCCOMP is LOW and 0Hx is selected by SIMP then 0HF is selected for the FLAT signal, and when 1Hx is selected by SIMP then 1HF is selected for the FLAT signal. This ensures that the FLAT and SIMPLE data selected for any comb filter is delayed by the same amount as the data processed through the comb filter to produce the COMB output. The final selection is the output required for the combed luminance and chrominance data. The output selection can be SIMPLE, COMB, FLAT-COMB, or FLAT. Generally COMB is selected based upon whether a luma or chroma comb was selected and the complementary output selects FLAT-COMB. In the YC and Y & CbCr data modes the FLAT signal selects the secondary data and SIMPLE or COMB can be used to select the primary signal. In these modes the bandsplit filter can be bypassed or used to remove low frequency noise from the chrominance signal if chroma was selected as the primary signal.
SIMP 2:1 MUX
A
B 4:1 MUX C Y Data
IPCF[1:0] OHF OHH OHL 3:1 MUX
D YMUX[1:0]
IPCF[1:0] 1HF 1HH 1HL IPCF[1:0] 2HF 2HH 2HL SIMP 2:1 MUX 3:1 MUX CMUX[1:0] A 3:1 MUX Adaptive Comb Filter
A: Comb B: Simple C: Flat - Comb D: Flat
B 4:1 MUX C Data
DLYF
-
C
3:1 MUX VideoB
D
65-22x5y-57
Figure 16. Signal Flow Around the Adaptive Comb Filter. REV. 1.0.0 2/4/03
47
TMC22x5yA
PRODUCT SPECIFICATION
The comb filter architecture performs chrominance or luminance comb filtering on PAL or NTSC video signals, by implementing one of sixteen independent chroma and luma comb filter algorithms. The highest level of the adaptive comb filter configuration is determined by the STA[3:0] register bits as shown in Table 3.
Table 3. Comb Filter Architecture
STA[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Comb Filter Description YC or Composite, PAL or NTSC, 3 line comb YC or Composite, NTSC, 3 line comb (0H & 1H) YC or Composite, NTSC, 3 line comb (1H & 2H) YC or Composite, NTSC, 2 line comb (0H & 1H) YC or Composite, NTSC, (2 line) field comb YC or Composite, NTSC or PAL, field comb YC or Composite, NTSC, (2 line) frame comb YC or Composite, NTSC, frame comb D1, Y or CBCR, 3 line comb D1, Y or CBCR, 3 line comb (0H & 1H) D1, Y or CBCR, 3 line comb (1H & 2H) D1, Y or CBCR, 3 line comb (0H & 2H) D1, Y or CBCR, (2 line) field comb D1, Y or CBCR, field or 2 line comb (0H & 1H) D1, Y or CBCR, (2 line) frame comb D1, Y or CBCR, Frame
several comb filter architectures. These comb filter architectures weight the three lines by varying degrees depending upon the degree of picture correlation between the inputs to the comb filter. The simple example in Table 4 shows how this process works, in which upper denotes error comparisons between the two lines stores and lower denotes error comparisons between the input and the first line store. The 0H, 1H, and 2H terms used in the mathematical description of the comb filter selection refer to the position with respect to the internal line stores. The 0H term is the undelayed input, 1H is the output of line store 1, and 2H is the output of line store 2. In this example a 3 line comb is implemented when in the flat areas of blue or yellow. However, when a difference between the inputs is detected the 3 line comb filter adapts to the 2 line comb filter whose inputs have the smallest difference. This illustrated on line n+4, at which time the comb filter adapts to inputs from 1H (blue) and 2H (blue) and ignores the 0H (yellow) inputs. In cases where there is a difference between all inputs to the comb filter, a 3 line comb filter is selected and the highest set of comb fail signals are sent to the XLUT input logic. This technique would work well if pictures only contained vertical transitions, which is obviously not the case. Therefore the weighting of these comb filter taps, (0H, 1H, and 2H), are rarely just the simple ratios shown in Table 4. It is worth noting that comb filters that use an even number of lines in the comb filter architecture produce chrominance and luminance signals that are vertically offset by one picture line, i.e. in the middle of the even number of lines used in the comb filter input. While comb filters that use an odd number of lines, in the comb filter architecture, the chrominance and luminance produced is referenced to the center, i.e. the middle line, of the comb filter. This approach can consequentially cause aliasing in decoding composite video signals containing high frequency diagonal transitions. The FAST register bit, when set LOW, filters the comb filter selection to decrease the sensitivity of the adaption algorithm. The second method completely disables the adaption between different comb filters, by setting the ADAPT[1:0] register bits accordingly, see Table 5.
The COMB signal can be produced in two ways. The first method uses the comb fail detection circuits to select one of
Table 4. Simple Example of an Adaptive Comb Filter Architecture
Error signals Line no. n+6 n+5 n+4 n+3 n+2 n+1 n Input col- upper or luma blue blue blue yellow yellow yellow black x 0 0 >0 0 0 x upper sat. x 0 0 0 0 0 x upper hue x 0 0 180 0 0 x lower luma x 0 >0 0 0 >0 x lower sat. x 0 0 0 0 >0 x lower hue x 0 180 0 0 >0 x Comb filter selection unknown without line n+7 [0H/4] + [1H/2] + [2H/4] [0] + [1H/2] + [2H/2] [0H/2] + [1H/2] + [0] [0H/4] + [1H/2] + [2H/4] [0] + [1H/2] + [2H/2] unknown without line n-1
48
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
In either of these methods, the "K" signal can be used to cross fade between the YCOMB and the SIMPLE bandsplit signals. The resulting comb filter equation can be expressed as: Combed Luma = Simple + (K * Combed High Frequency Luma) Combed Chroma = Simple - (K * Combed High Frequency Luma) In the case of the chroma comb, the weighted combed high frequency luma is subtracted from the SIMPLE high pass filter output to produce the combed chroma signal, and for luma comb filters the weighted combed high frequency luma is added to the SIMPLE low pass filter output to provide the combed luminance signal.
errors in the demodulated picture. In this example, the chrominance signal would be demodulated with a 180 degree phase error. Unlike the "simple" decoder technique any errors in the comb filter decoding produce components that if re-encoded will never reproduce the original composite video waveform. It is therefore imperative that the number and magnitude of comb fails be kept to its absolute minimum. This is not possible with non-adaptive comb filter architectures, and all vertical and diagonal transitions in the picture will cause irreversible picture degradation. For this reason, all the TMC22x5yA comb filter decoders implement an adaptive comb filter architecture. To aid in this decision making process, comprehensive comb fail signals are generated and fed to a user-programmable lookup table (XLUT). The output of the lookup table provides the control for the cross fade between the comb and simple bandsplit decoder.
Comb Fails
The inputs to the comb filter are monitored to detect discontinuities that would cause the comb filter operation to fail. Whenever a significant failure is predicted, the comb filter architecture is modified and an error signal proportional to the discontinuity is produced. For flat areas of color, it is a relatively simple to produce an error signal that switches between the outputs of the comb filter and the simple band split filter without visibly softening the picture horizontally or vertically. However, as horizontal frequencies increase during vertical transitions, so the decision for switching between the comb and simple bandsplit decoder becomes more complex. A line based comb filter can separate the luma and chroma signals from line repetitive composite video signals, with no loss of luma or chroma bandwidth. However, if there is a vertical transition, i.e. a change from one scan line to the next, as shown for a NTSC two line comb in Figure 17, a comb fail occurs. The comb fail shown in Figure 17, clearly illustrates the resulting vertical smearing of the luma and chroma signals. In addition to the smearing, the resulting phase of the chrominance signal with respect to the burst can cause hue
Comb Fail Detection
The traditional approach of using the low frequency data to look for vertical luma transitions, and rectifying the high frequency data to estimate vertical transitions in the chroma provides adequate comb fail detection. However, chroma signals that are equal in magnitude but 180 degrees apart in phase, which can also have a small difference in luma level, for example green and magenta, can produce undetected comb fails in the comb filter output. To overcome problems with simpler comb fail measurement techniques, the TMC22x5yA generates an array of patented comb fail and comb filter control signals. To produce these signals each input to the comb filter is passed through a simple bandsplit decoder. This provides a luma signal from the low frequency portion of the comb filter input, and the hue (phase) and saturation (magnitude) from the high frequency portion of the comb filter input. These signals are compared and the differences in luma, hue, and saturation are used to determine the type of comb filter used to generate the YCOMB signal and to provide the cross fade control signal "K". The "K" signal can be weighted within the XLUT lookup table, allowing the user to tailor the comb filter response to their system requirements.
65-22x5y-58
Figure 17. Example of a Comb Fail Using a NSTC Two Line Comb Filter REV. 1.0.0 2/4/03
49
TMC22x5yA
PRODUCT SPECIFICATION
Generation of the Comb Fail Signals
Luma Error Signals
The signals from the 3 low pass filters, 0HL, 1HL, and 2HL are subtracted from one another to produce an error signal proportional to the luma comb fail. The resulting signals (0HL - 1HL), produces LYE, and either (1HL - 2HL) in NTSC or (0HL - 2HL) in PAL produces UYE. The LYE and UYE luma error signals are rectified if negative. In cases where the luminance component is constant, the error will be zero. Where the luminance goes from black to white over 2 lines, the error signal will go to its maximum value. The luma error signals can be doubled to facilitate inputs with low picture levels by setting the YESG register bit HIGH. The resulting signal is clipped to ensure no overflow occurs
provide the phase and magnitude of the in-phase and quadrature components of the high frequency data. These components are compared to determine the difference in phase and magnitude between 0H & 1H in all configurations, LME and LPE, and between 1H & 2H in NTSC or 0H & 2H in PAL, UME and UPE. The magnitude error signals can be doubled to facilitate inputs with low picture levels by setting the CESG register bit HIGH. The doubled magnitude error signals are limited to ensure no overflow occurs. The algorithm used to separate the quadrature components depends upon the relationship between the normalized subcarrier frequency and the number of pixels per line. This algorithm is preset for either a NTSC/M or PAL/I subcarrier frequency and a pixel data rate of 13.5MHz. It is therefore necessary to compensate for other pixel data rates by selecting the appropriate default using the CEST[1:0] register bits.
Hue and Saturation Error Signals
In the past, comb decoders have relied upon comparing the difference in chroma magnitude between two lines to determine a comb fail. In fact, this chroma signal is normally the output of the high-pass or band-pass filter, and therefore contains all the high frequency luminance information as well. As this signal was never demodulated, the sign bit was immaterial and was used only to rectify the chroma signal. This allowed chroma signals which where equal in magnitude but opposite in phase, and high frequency luminance signals, to fool the comb fail circuit. The TMC22x5yA uses a new, innovative approach to overcome this problem. To detect comb failures in the highfrequency portion of the video signal the outputs from the three high-pass filters, 0HH, 1HH, and 2HH, are passed through simple demodulators. The outputs from which
Picture Correlation
The degree of picture correlation depends upon the differences between the UYE, UME, and UPE upper error signals and the LYE, LME, and LPE lower error signals, and is measured as a percentage of full scale error. In flat fields of color you would have 0% error in picture correlation, however in sharp vertical transitions say between yellow and blue you would have large % errors between UYE and LYE and between UPE and LPE, while there would be 0% error between UME and LME.
Adapting the Comb Filter
In NTSC it is possible to switch from a 3 line comb to a 2 line comb, and then to a simple decoder output. The 3 line comb to 2 line comb switch can be disabled, forcing the 3 line comb to switch directly to simple. The switching between these two comb architectures is independent of the
OHL 1HL 2HL
Luma Comparison
UYE LYE
YESG
YWBY
OHH Chroma Demodulation & Rectangular to Polar Conversion
Hue Comparison
UPE LPE
1HH
2HH
Saturation Comparison
UME LME
CESG CEST[1:0]
CSETBY
65-22x57-59
Figure 18. Generation of Upper and Lower Comb Fail Signals
50
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
ADAPT[1:0]
YCSEL
FAST
UYE LYE
2:1 MUX Filter Comb Fail Logic
CFSEL[3:0]
UPE LPE
YERR PERR MERR
UME LME
STA[3:0]
CAT[1:0]
65-22x5y-60
Figure 19. Comb Filter Selection
mix signal, K. For 3-line Y/C comb filters, an external 1H delay is required in the uncombed channel to compensate for the comb filter delay. This principle is equally true for NTSC frame and field based comb decoders. The feature is not available for any of the PAL comb filter architectures. The Comb filter Adaption Threshold register bits CAT[1:0] determine if 5%, 15%, 25%, or 50% errors in picture correlation is required to adapt the NTSC comb filter. In NTSC, due to the 180 degree advance in subcarrier phase per line, it is possible to switch between the 3 line comb and the choice of either the upper two line comb or the lower two line comb. If this switching occurs on a pixel by pixel basis the picture will contain vertical alias components. This artifact can be reduced by either setting the FAST register bit LOW, which filters the comb filter selection, and/ or setting the CAT[1:0] register bits to a higher percentage threshold. The comb filter adaption is further controlled by the ADAPT[1:0] register bit selection, when the COMB[3:0] register bits select a 3 line comb. These bits control if the comb filter adapts from a 3 line comb to the best of the upper or lower 2 line combs, from a 3 line comb to just the lower 2 line comb, performs a fixed 3 line comb, or implements a best of two 3 line combs in PAL. If the COMB[3:0] register bits select one of the 2 line comb filters, the ADAPT[1:0] register bits are ignored, and no adaption is implemented. The CFSEL[1:0] signal, shown in Figure 19, controls which comb filter is selected on a pixel by pixel basis, and can be externally monitored by reading CFSTAT[1:0] in register 4Bh.
Table 5. Adaption Modes
ADAPT[1:0] 00 01 Function Adapts to the best of 3 types of line based comb filters in NTSC only. 3 line (tap) comb always adapts to lower 2 line (tap) comb, when the 3 line (tap) comb fails. Normally used with NTSC field and frame based comb filters. 3 line (tap) comb only. Never adapts to a 2 line(tap) filter. The higher set of comb filter error signals are sent to the XLUT. NTSC or PAL comb filter. Adapts to best of two 3 line comb filters in PAL only.
10
11
XLUT
The comb fail signals control both the comb filter adaption and the cross fade between the adaptive comb filter output YCOMB and the SIMPLE bandsplit signal. Which of the fail signals is fed to the XLUT is determined by which comb filter is selected in NTSC. When a 3 line comb filter is selected, the larger set of error signals are sent to the XLUT, when a upper 2 line comb is selected UYE, UME, and UPE error signals are selected, and when a lower two line comb filter is selected the LYE, LME, and LPE error signals are selected.
REV. 1.0.0 2/4/03
51
TMC22x5yA
PRODUCT SPECIFICATION
XFEN
YERR PERR MERR
XLUT Input Select
X[7:0]
XLUT
2:1 MUX Filter
K[4:0]
65-22x5y-61
XIP[1:0]
Figure 20. XLUT Input Selection
For PAL comb filters the LYE, LME, and LPE errors signals are always selected by default. In this way the error signals into the XLUT always represent the comb filter being implemented. The resolution of the error signals selected is controlled by the XIP[1:0] register bits as shown in Table 6: XLUT Input Selection. The position of these error signals on the XLUT input address X[7:0] is also shown.
Table 7. XLUT Output Function. (cont.)
XLUT OUTPUT 16 : 29 30 31 : 29 30 32 - 100% Comb K 16 - 50% Bandsplit, 50% Comb
Table 6. XLUT Input Selection
XIP[1:0] 00 Function 2 bits of phase error (X[7:6]), 3 bits of chroma (X[5:3]) and luma magnitude error (X[3:0]). 4 bits of chroma (X[7:4]) and luma magnitude error (X[3:0]). 3 bits of phase error (X[7:5]), 3 bits of chroma magnitude error (X[4:2]), and 2 bits of luma magnitude error (X[1:0]). 4 bits of phase error (X[7:4]) and chroma magnitude error (X[3:0]).
The special function assigned to K = 0 is programmed into the XSF[1:0] register bits, as shown in Table 8.
01 10
Table 8. XLUT Special Function Definitions
KIP1-0 00 01 10 11 XLUT special function selection Y comb simple flat with notch flat with notch C simple comb simple comb
11
The selected comb fail signals are translated by the userprogrammed configuration within the 256*5 XLUT into the mix signal (K) which controls the 30 levels of cross-fade between the weighted comb filter and the band split filters. The 1 to 31 mix signal is modified on the input to the crossfade to produce a 0 to 32 control signal, as shown in Table 7.
Table 7. XLUT Output Function.
XLUT OUTPUT 0 1 2 3 : K Special function (e.g. luma comb and HPF on chroma) 0 - 100% Bandsplit 2 3 :
The "Flat with notch" selection passes the FLAT input through onto the luminance channel and selects the notch filter, centered at 0.25 of the normalized clock frequency. This mode is therefore only useful with inputs at 4*Fsc or in cases when a notch at 0.25 of the normalized clock frequency is adequate for application. The XLUT output, is fed through a bypassable low-pass filter KLPF to avoid switching between comb and simple decoders on a pixel by pixel basis. When the special function is selected (K = 0) the input to the KLPF is held and the filter is automatically bypassed. The output of the XLUT can be externally monitored by reading XOP[4:0] in register 4Bh.
52
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
.
Gaussian LPF - Chrominance sin(wt) Gaussian LPF V Data U Data
65-22x5y-62
Burst Locked Loop
cos(wt+)
Figure 21. Block Diagram of Digital Burst Locked Loop
Digital Burst Locked Loop
The digital burst locked loop provides sine and cosine signals which are phase locked to the incoming burst signal. These sine and cosine signals are used to demodulate the chrominance data, producing the U and V color-difference signals. The U data are phase-referenced to sin(wt) and the V data to cos(wt). The demodulated signal is passed through a low pass filter to remove signals at twice the subcarrier frequency. The magnitude of the U and V data within the demodulated burst signal provides the error signal which, after filtering, is used to adjust the frequency and/or phase of the subcarrier DDS. The output of the subcarrier DDS is translated into sine and cosine signals in ROM-based lookup tables. The PALODD signal is low on lines without the 180 degree phase advance in the modulated V signal, termed NTSC lines, and high for lines with the 180 degree phase advance, termed PAL lines. This signal is used in the burst locked loop to advance the phase of the cosine table on PAL lines. PALODD is always low for NTSC.
Frame Bit
NTSC The middle bit (frame bit) of the field count is determined, by the phase of the subcarrier on a given pixel and on a given line. The signal used to determine this is NFDET (New Field DETect), and occurs when the line count is zero and the pixel count is one of four programmable pixel positions, zero, one, two, or three. PAL The frame bit in PAL is detected through the Bruch blanking sequence. The error signal control circuit generates a color kill flag whenever a line is detected without a burst. It is therefore possible to compare this signal with specific line idents to determine the field sequence in both PAL-I and PAL-M. A set of specific patterns determine the correct phase of FID1; if any of these patterns is detected then FID1 is forced to a known state and then flywheels until the next fixed pattern is detected.
Color Kill Counter
The demodulated U and V components are compared to a programmable burst level threshold. If both the U and V data fall below this threshold, a color kill flag is set high. The color kill counter is incremented once per line if the color kill flag is high. If the count reaches 127 within one field, the color kill circuit becomes active during the next field group. When this occurs, the input video will be passed unaltered on the luminance channel and the color difference signals will be set to chroma black. The color kill signal remains active until a field with less than 127 lines without burst is encountered, at which time, during the next vertical blanking period, the decoder is reset. The operation of the color kill logic can be monitored externally by reading the MONO register bit in register 44h. The MONO bit is HIGH for composite and YC video signals and LOW for monochrome signals.
Field Flag, FLD
Table 9. PAL-B,G,H,I Bruch Blanking Sequence
Internal line # 5 309 6 309 5 309 6 309 Burst present No No Yes No Yes Yes No Yes Internal frame # 0 or 2 0 or 2 0 or 2 0 or 2 1 or 3 1 or 3 1 or 3 1 or 3 Internal field # 0 or 4 0 or 4 1 or 5 1 or 5 2 or 6 2 or 6 3 or 7 3 or 7
The frame bit is low for frames 0 and 2 and high for frames 1 and 3.
The FLD signal is the lsb of the field count FID2-0 and is LOW for fields where the first vertical sync occurs in the first half of the line and is HIGH for fields when it occurs in the second half of the line. This signal is synchronized with the frame and color frame flags in the FID generator.
REV. 1.0.0 2/4/03
53
TMC22x5yA
PRODUCT SPECIFICATION
Table 10. PAL-M Bruch Blanking Sequence
Internal line # 7 258 7 259 7 258 7 259 Burst present No Yes No No Yes No Yes Yes Internal frame # 0 or 2 0 or 2 0 or 2 0 or 2 1 or 3 1 or 3 1 or 3 1 or 3
0
Internal field #
Attenuation (dB)
-10 -20 -30 -40 -50 -60 -70 0.00 0.10 0.20 0.30 0.40 Demodulator Filter 2
65-22x5y-63
0 or 4 0 or 4 1 or 5 1 or 5 2 or 6 2 or 6 3 or 7 3 or 7
Demodulator Filter 1
Normalized Frequency
The frame bit is low for frames 0 and 2 and high for frames 1 and 3.
Figure 22. Gaussian Low Pass Filters
PAL Color Frame Bit
Attenuation (dB)
0 -2 -4 -6 -8 -10
0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16
The PAL color frame bit is the msb of the field count, FID2. In NTSC this is always low, as NTSC has only a 4 field sequence. For both PAL-I and PAL-M inputs, the PAL color frame bit is determined in the same way the frame bit is determined in NTSC, by using the phase of the subcarrier on a given pixel and on a given line.
Demodulator Filter 1
Demodulator Filter 2
Hue Control
One of two programmable 16 bit system phase offsets can be added to the subcarrier oscillator between SAV and EAV. The selection is made by the BUFFER pin. This feature allows the user to change the picture hue on known frames without affecting the burst locked loop.
Normalized Frequency
Figure 23. Gaussian LPF Passband Detail Bypassing the Chrominance Demodulator
System Monitoring of the Burst Loop Error
The burst loop error signal is stored once per line in an 8 bit register that can be accessed over the microprocessor port. This allows the user to check for non-mathematical PAL inputs and to the change the decoder architecture from framebased to line-based or simple decoder depending on this information.
Demodulation Low Pass Filter
The demodulation of the chrominance signal needs to be bypassed when the decoder is processing CBCR component data or when a YC output is required. The bypass operation is controlled by the DMODBY register bit.
Bypassing the Demodulation Low Pass Filter
There are two different demodulation low pass filters that can be selected under software. For PAL inputs with normalized subcarrier frequencies greater than 0.3 of the sampling frequency, it is recommended you use "demodulator filter 2" to stop aliasing of the second harmonic of the demodulation chrominance signal and the baseband color difference signals. Gaussian filters are used for both demodulation filters as they have no negative coefficients and therefore have no undershoots or overshoots which could cause in-band ringing.
The demodulation low pass filter needs to be bypassed when processing CBCR component data or when a YC output is required. The CBCR data can also be passed through the Gaussian filter if the bandwidth needs to be reduced. The bypass operation is controlled by the GAUBY register bit.
Chrominance Coring
Chrominance coring, when active, sets the lsbs of the chroma channel (below a programmable threshold) to zero.
VMCR5 Operation When VMCR5 is HIGH, the decoder will grab one line of
video in LSTORE1. This effectively removes the comb filter from the decoding process, and the comb filter output is forced to simple mode.
54
REV. 1.0.0 2/4/03
65-22x5y-64
0.50
PRODUCT SPECIFICATION
TMC22x5yA
Output Processor
Mixed Sync
X
SGx[9:0] Adaptive Luma Notch Filter
+ +
YOFF[8:0] Output Formatter B/Cb Data R/Cr Data G/Y Data
Y Data VIDEOB LPF 256 240
-
Clamp Circuit
-
PED[7:0]
X X
ANT[1:0] YSEL ANEN YGx[9:0]
CLMP[1:0] VCLPEN U Data
X
UGx[10:0]
Fixed (B-Y) Gain Stage
X
Fixed (R-Y) Gain Stage
65-22x5y-65
V Data
X
VGx[10:0]
Figure 24. Output Processor Block Diagram
Clamp Circuit
A clamp pulse generated by the Burst Gate signal is used to grab either a sample of the low-pass-filtered luma during the video back porch, the signal on VIDEOB, or one of two internally generated levels. The selection is made by the CLMP[1:0] register bits.
clamp pulse can be used to control where an analog clamp circuit grabs the analog reference to establish the correct voltage level into the A/D. Usually the clamp pulse is generated on the back porch or duing the sync tip of a video line.
Adaptive Notch Filter
Table 11. Blanking Level Selection
CLMP[1:0] 00 01 10 11 Blanking Selection Internal 240 level Internal 256 level External VIDEOB Input Internal LPF Output
The blanking level is subtracted from the decoded luma. If the sign is negative, the result is assumed to be mixed sync and is passed through a delay and into the sync gain stage within the output matrix. If the sign is positive, the result is assumed to be pure luma (blanking to peak white) and is fed to the pedestal removal circuit.
The PAL line-locked comb decoder can never provide perfect subcarrier cancellation due to the 25Hz offset in the subcarrier frequency. This 25Hz offset causes residual and phase modified subcarrier to be left on the luminance signal which can produce a visible dot crawl on flat areas of color. However, for all comb filter structures, the quality of the comb depends on the quality of the sampling clock, as line to line clock jitter will also cause small phase changes between the inputs to the comb filter. It is therefore possible that NTSC comb decoders may also require some coring of the luma output. To meet the wide range of sample frequencies that the decoder must deal with two separate coring filters are selectable. The luma signal from the pedestal stripper is compared against the preceding pixel to detect the magnitude change between pixels. This magnitude difference will be almost zero for flat areas of picture, and large for high frequency changes in the picture. The magnitude difference is compared to one of four programmable thresholds. The programmable threshold is selected by the ANT1-0 register bits as shown in Table 12.
Pedestal Removal
The 8 bit programmable pedestal is subtracted from the pure luma signal. The negative super black signals are clipped to zero when register 0Ah bit 4 is set LOW, or the super black signals are passed through the luma scalar when register 0Ah bit 4 is HIGH.
Table 12. Adaptive Notch Threshold Control
ANT1-0 00 01 10 11 Magnitude difference less than 16 less than 12 less than 8 less than 4
Clamp Generator
The TMC22x5yA has the unique option to output a negative going clamp pulse that is 0.5 sec wide. This pulse can be output on the AVOUT pin by placing a HIGH on register 24 bit 7. The pulse's position relative to HSYNC can be varied by register 25. This value is the number of PCK clock cycles after an HSYNC that the pulse will be output to the pin. The
REV. 1.0.0 2/4/03
55
TMC22x5yA
PRODUCT SPECIFICATION
If either of the error signals indicates that the magnitude difference is above the programmed threshold, or if ANEN is LOW, the adaptive notch filter is bypassed. The output of the adaptive notch filter is rounded to 8 or 10 bits, or the luma data that bypasses the coring filter is truncated to 8 or 10 bits depending upon the CORO register bit.
0 -10 Attenuation (dB) -20 -30 -40
65-22x5y-09
Programmable U Scalar
The U scalar (UGx) provides the weighting required to produce (B-Y) or CB from the demodulated U signal. hence (B-Y) = UGx * U where UGx = gain / 0.493, and CB = UGx * U
Adaptive Notch Filter 32
Adaptive Notch Filter 1
where UGx = (gain * 448) / Umax UGx has a scaling range of 0 to (2047/256).
-50 -60 -70 0.00 0.10 0.20 0.30 0.40 Adaptive Notch Filter 2
Programmable V Scalar
The V scalar (VGx) provides the weighting required to produce (R-Y) or CR from the demodulated V signal. hence (R-Y) = VGx * V where VGx = gain / 0.877, and
Normalized Frequency
Figure 25. Adaptive Notch Filters
Luma Notch Filter
The simple luma notch filter is centered at 0.25 of normalized frequency, it therefore intended for use only in the subcarrier mode (4 * fSC) and for limited use with 13.5MHz NTSC as the subcarrier sits at 0.265 of normalized frequency. The notch filter is enabled by setting the NOTCH register bit HIGH.
0 -10 Attenuation (dB) -20 -30 -40
65-22x5y-67
0.50
CR = VGx * V where VGx = (gain * 448) / Vmax VGx has a scaling range of 0 to (1023/256).
Programmable Y Scalar
The Y scalar (YGx) provides the scaling for the luminance signal if the output is YCBCR, or controls the magnitude of the RGB output along with the U scalar and V scalar. It is not possible to control the magnitude of the RGB signals independently. YGx has a scaling range of 0 to (1023/256).
-50 -60 -70 0.00 0.10 0.20 0.30 0.40
Programmable MS Scalar
The sync scalar (SGx) provides the scaling for the sync signal if the output requires sync on RGB. The programmed sync scaling factor is used during the horizontal and vertical burst blanking periods. During the active lines, the luma scaling factor is used to allow scaling of "super blacks" etc., which will be passed down the mixed sync path because they fall below the clamp level. SGx has a scaling range of 0 to (1023/256).
Normalized Frequency
Figure 26. Luminance Notch Filter
Matrix
The magnitude of the decoded luminance and color difference signals will vary, not only with the standard, but also with the input mode. For this reason the output matrix contains programmable multipliers, and not just fixed scaling factors. The following sub sections explain the different scalar in the output matrix. The gain term in the Y, mixed sync, U and V scalar is the same - only the weighting makes them different. The scalar are capable of independently providing 6dB of gain if required.
0.50
Fixed (B-Y) and (R-Y) Scalars
These two scalars are zero when the output is YCBCR and provide the (B-Y) and (R-Y) weighting when the output is RGB. These are fixed scaling factors and are derived from the following equations. (G-Y) = - [(0.299/0.587) * (R-Y)] - [(0.114/0.587) * (B-Y)] or (G-Y) = - [(1043/2048) * (R-Y)] - [(398/2048) * (B-Y)]
56
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Y Offset
The 8 bit Y offset adds any offset required in the Y or RGB data outputs. For example 64 (16) for the 64 (16) to 940 (235) 10 bit (8 bit) 601 outputs. When the output is YCBCR this offset is applied to the luminance data only. The Y offset also provides the blanking level for RGB outputs with syncs. Color Red Blue Black
Decoder Output Y 325 163 64 CB -150 448 0 CR 447 -73 0
CCIR 601 Spec Y 326 164 64 CB -151 448 0 CR 448 -72 0
Matrix Limiters
The different limiters are listed below, 10 bit data is assumed.
PAL digital composite input and RGB (0-1023) outputs: Color White Yellow Cyan Green Magenta Red Blue Black Y 572 507 401 336 236 171 65 0 U 0 -250 84 -165 165 -84 250 0 V 0 57 -352 -295 295 352 -57 0
Table 13. Matrix Limiters
LMT1-0 00 01 10 11 Comments RGB output format, limited from 0 to 1023 YCBCR output format, Y limited from 0 to 1023 and CBCR limited to +/- 511. RGB output format, limited from 64 to 940 YCBCR output format, Y limited from 64 to 940 and CBCR limited to +/- 448
The nominal scaling factors are simply:
Examples of Output Matrix Operation
From the SMPTE-170M specification: Color White Yellow Cyan Green Magenta Red Blue Black YCBCR data ranges are: Y data range is 64 to 940 (876) CBCR data ranges are 64 to 960 (+/- 448) Matrix programming: YGx = (876 / 540) = 1 + (159/256) UGx = (448 / 236) = 1 + (230/256) VGx = (448 / 332) = 1 + (89/256) YOFF = 64 PED = 44 Decoder Output Color White Yellow Cyan Green Magenta Y 939 841 678 578 426 CB 0 -448 150 -296 296 CR 0 73 -447 -376 376 CCIR 601 Spec Y 940 840 678 578 426 CB 0 -448 151 -296 296 CR 0 72 -448 -375 375 Y 584 523 423 361 267 205 105 44 U 0 -236 79 -156 156 -79 236 0 V 0 54 -332 -278 278 332 -54 0
YGx = 1023/572 = 1 + (202/256) UGx = (1023/572)*(1/0.492) = 3 + (163/256) VGx = (1023/572)*(1/0.877) = 2 + (10/256) YOFF= 0 PED = 0 Color White Yellow Cyan Green Magenta Red Blue Black G 1023 1023 1023 1023 0 0 0 0 R 1023 1023 0 0 1023 1023 0 0 B 1023 0 1023 1 1022 1 1023 0
It is also possible with the architecture supplied to use the limiters on the output of the matrix to clip the output video deliberately by using a slightly larger gain than is required. The Y_Offset can achieve the same by setting its value to be one lsb less than the minimum clip level.
Buffer Registers
The BUFFER pin allows the user to externally switch between two sets of internal registers that have the same function. This register buffering allows the matrix gain, picture hue, and luma offset to be changed at a known time relative to the input data. Registers 17 to 1D are selected when the BUFFER pin is LOW and registers 27 to 2D are selected when the BUFFER pin is HIGH. If the msb of the decoder product code DPC2 is LOW, an 8 bit decoder has been selected and the bottom 2 bits of registers 17 to 1A and 27 to 2A are forced to zero.
REV. 1.0.0 2/4/03
57
TMC22x5yA
PRODUCT SPECIFICATION
Simple Luma Color Correction
If the YBAL register bit is set HIGH, and the luma data reaches or exceeds the luma limits, there should be no CBCR or UV data at that time; therefore the color data are set to ZERO. If YBAL is set LOW then the CBCR/UV data are unaffected by the luma data.
CBSEL, to produce the multiplexed CBCR data stream at the PCK clock rate. If the input was initially D1 then the dropped samples will be the interpolated samples produced by the chroma interpolation filter. If however the CBCR data are simply weighted UV data then the sample dropped demodulated color difference signals (UV) will alias around 0.25 of the normalized sample frequency.
CBCR MSB Inversion
The msb of the CBCR data can be inverted by setting the MSBO register bit HIGH. As this would affect the chroma blanking level, this circuit appears at the output of the MATRIX circuit.
Multiplexed YCBCR Output (TRS Words Inserted)
When both the CDEC and YUVT register bits are HIGH the Y, CB, and CR component data are multiplexed into a single 27MHz (PXCK) data stream with embedded TRS words. The TRS words are generated based on the HSYNC or VSYNC pulses provided to the decoder, and the internally derived horizontal blanking (HBLK), vertical blanking (VBLK), and the field flag (FLD). This mode of operation is only available if a line locked PXCK clock, at 27MHz, is provided. The TRS words will be generated with respect to the HSYNC\ signal as per the ANSI/SMPTE 125M-1992 and CCIR 656 specifications.
Output Rounding
For compatibility with 8 bit systems, the output of the matrix can be rounded to 8 bits by setting the RND8 register bit HIGH.
Output Formats
RGB Outputs
The RGB data are simply passed through to the decoder output. When the DRSEN register bit is HIGH the DRS data are inserted into the green data path only.
YUV Outputs
YC Outputs
The YC data are passed through to the decoder output. When the DRSEN register bit is HIGH the DRS data are inserted into the luminance data path only. The luminance appears on G/Y, chrominance is on B/U and the R/V output is set to zero, by setting the V_scalar to zero.
The YUV data are simply passed through to the decoder output. When the DRSEN register bit is HIGH the DRS data are inserted into the luminance data path only.
YCBCR Outputs The YCBCR data can be output in 3 ways, depending upon
The LDV Clock
The decoder can accept clocks at either the pixel clock rate (PCK) or at twice the pixel clock rate (PXCK). In the cases where the clock provided is PXCK, for example the genlock mode, the output data still needs to be at the PCK clock rate. To aid in the design of external circuitry a LDV clock is provided if the LDVIO register bit is LOW, if LDVIO is HIGH then the LDV pin becomes an input for an external clock. If an external LDV clock is employed the user must ensure that the rising edge of the external LDV meets the specified setup and hold times relative to the input CLOCK pin. The selection of which clock to use on the decoder output is set by the OPSEL register bit. When OPSEL is set LOW the output is clocked at the same rate as the clock on the CLOCK pin, and when OPSEL is set HIGH the output is clocked by the internal or external clock on the LDV pin.
the CDEC, F422, and YUVT register bits. These output modes are summarized in . When CDEC is HIGH and F422 is HIGH, the G/Y output is set to 64 and the B/U output is set to 512 between the EAV TRS data word and the first preamble word of the SAV TRS, i.e. during the digital horizontal blanking period. When YUVT is HIGH, R/V is set to 512, 64, 512, 64, etc., starting after the EAV TRS data word and finishing before the SAV preamble.
Decimating CBCR Data
Whenever the CDEC register bit is set HIGH the B/U and R/V data are simply sample dropped, with respect to
Table 14. Output Format
CDEC 0 1 1 1 YUVT x 0 0 1 F422 x 0 1 x G/Y G or Y Y Y Y B/U B or CB CB CBCR CBCR R/V R or CR CR 0 D1 data Comments [4:4:4] data [4:2:2] data [4:2:2] data [4:2:2] data & D1 output
58
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Sync Pulse Generator
The vertical and horizontal references to the decoder can be from external VSYNC and HSYNC pulses, decoded from TRS and TRS-ID words, or from the internal sync separator which extracts the sync information from the digitized input video. The sync pulse generator (SPG) provides all the clock and enable pulses required to synchronize the decoder operation to the incoming video signal. These pulses are described below, along with the microprocessor data required to control them.
HBLK (Horizontal Blanking Period)*
The horizontal blanking period is LOW between the start of SAV and the end of EAV. This signal is used in several places: a) To clear the SYSPH offset when LOW, this is required for correct operation of the subcarrier phase locked loop, b) To aid in the comb filter management, c) To remove the burst envelope on the demodulated UV data, d) To remove the syncs on the BLUE and RED outputs.
BBLK (Vertical Burst Blanking Period)
Internal Field and Line Numbering Scheme
The internal line numbering of the digital decoder differs from the standard video line numbering as shown in the following tables. The internal line numbers for a 3 line comb advance the numbering by 1 line with respect to the input, but are identical with respect to the internally one line delayed decoded video.
The vertical burst blanking blanks the lines with no burst from the burst phase locked loop. This signal is decoded from the line ident, LID4-0, and is modified by the video standard and the field count.
MBLK (Mixed Blanking)
Table 15. NTSC Field and Line Numbering
Standard Field # 1&3 1&3 2&4 2&4 Standard Line # 1-3 4 - 263 264 - 265 266 - 525 Internal Field # 1&3 0&2 0&2 1&3 Internal Line # 260 - 262 0 - 259 260 - 261 0 - 259
This signal is used in the matrix to switch between the sync scalar and the luma scalar. The MBLK signal is active whenever HBLK is active or becomes active when VBLK becomes active. MBLK is also active in PAL on line 310 when both VACT1 and FLD are HIGH and in NTSC and PAL M on line 259 when VACT2 is HIGH and FLD is LOW.
FLD*
The FLD is LOW for field 1 and HIGH for field 2.
LID4-0*
Table 16. PAL B,G,H,I Field and Line Numbering
Standard Field # 1&5 2&6 3&7 4&8 Standard Line # 1 - 312 313 - 625 626 - 937 938 - 1250 Internal Field # 0&4 1&5 2&6 3&7 Internal Line # 0 - 311 0 - 312 0 - 311 0 - 312
The line ID signals are used in the vertical comb filter management to control the comb filter on the leading and trailing lines of active video around the vertical blanking period, to start and stop the VINDO operation, and in generating the vertical blanking and burst blanking periods.
VACT2*
VACT2 is HIGH during the second half of all active lines.
GRABF*
The GRABF signal goes HIGH when the internal field count is equal to the programmed field number for the GRAB operation. f a pixel grab is being, this signal is held HIGH to not inhibit the GRABS signal on each line.
GRABL*
Table 17. PAL M Field and Line Numbering
Standard Field # 1&5 2&6 3&7 4&8 Standard Line # 1 - 262 263 - 525 1 - 262 263 - 525
*
Internal Field # 0&2 1&3 0&2 1&3
Internal Line # 0 - 261 0 - 262 0 - 261 0 - 262
The GRABL signal goes HIGH when the internal line count is equal to the programmed line number for the GRAB operation. If a pixel grab is being performed, this signal is held HIGH to not inhibit the GRABS signal on each line.
GRABP*
The GRABP signal goes HIGH when the internal pixel count is equal to the programmed pixel number for the GRAB operation.
DVSYNC and DHSYNC (Output Pins)
HSTBG (Burst gate)
The burst gate starts the 16 clock period average of the demodulated burst envelope. The position of the burst gate is programmed into a register as the number of clock periods from the falling edge of sync to the burst envelope.
*
Signal is available over the microprocessor data bus.
The DVSYNC and DHSYNC signals are active when GCR2 is LOW. When GCR2 is HIGH these signals are three stated. Three line comb based decoders have an inherent line delay, therefore the input VSYNC and HSYNC signals can not be just delayed by a few registers and output as DVSYNC and DHSYNC: they need to be delayed by one complete line. In all other comb filter configurations the DVSYNC and
REV. 1.0.0 2/4/03
59
TMC22x5yA
PRODUCT SPECIFICATION
DHSYNC are referenced to the input data (0HFLAT) and not the output of the LSTORE1, i.e. 1HFLAT. The duration of the DVSYNC signal is fixed to one line and the duration of the DHSYNC signal is 64 clock periods. Both these signals are generated by the internal horizontal and vertical state machines. The falling edge of these signals relative to the data matches the requirements of the TMC22x91 family of digital encoders.
AVOUT Active Video (Output Pin)
Table 19. Vertical Burst Blanking Period
Internal field no NTSC 0,2 1,3 PAL 0&4 1&5 2&6 3&7 PAL-M 0&4 1&5 2&6 Internal line no 0-5 259 - 261 0-6 260 - 262 0-5 309 - 311 0-5 309 - 312 0-4 310 & 311 0-6 310 - 312 0-7 259 - 261 0-7 259 - 262 0-6 258 & 261 3&7 0-6 260 - 262
LID4-0 List of Line Idents
The decoder produces an active video signal starting 4 PCK before the programmed start of active video and ending 4 PCK after the programmed end of active video. This signal is used in both the video mixer (TMC22x8x) family and the digital encoder (TMC22x9x) family. The end points of this signal are flagged by the internally generated SAV and EAV signals.
VBLK (Vertical Blanking Period)
**
The vertical blanking period conforms to the CCIR 656 specification for D1 component data streams. This signal is decoded from the line ident, LID4-0, and is active low.
Table 18. Vertical Blanking Period
Internal field no NTSC 0,2 1,3 PAL 0, 2, 4, & 6 1, 3, 5, & 7 PAL-M 0, 2, 4, & 6 1, 3, 5, & 7 Internal line no 0-5 260 & 261 0-6 260 - 262 0 - 21 310 & 311 0 - 22 311 & 312 0-5 260 & 261 0-6 260 & 262
BBLK (Vertical Burst Blanking Period)
The line numbers required to produce all the decoder control signals are summarized in
Table 20. Table of Line Idents, LID[4:0]
Line no: 0 1-4 5 6 7 8 9 - 16 17 18 19 - 21 22 23 24 25 - 257 258 259 LID4-0 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
The vertical burst blanking blanks the lines with no burst from the burst phase locked loop. This signal is controlled by the video standard and the field count. The burst blanking signal is active low.
**
Signal is available over the microprocessor data bus.
60
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Table 20. Table of Line Idents, LID[4:0] (cont.)
Line no: 260 & 261 262 263 - 307 308 309 310 311 312 LID4-0 10 11 12 13 14 15 16 17
STS: The number of pixels between sync pulses STB: The number of pixels between the nominal mid point of sync and the start of the 16 pixel burst gate. This value is modified depending upon the mode of operation.
Table 21. Timing Offsets
Standard x x x PAL NTSC x Mode Genlock Line locked Subcarrier D2 mode D2 mode D1 mode Offset required -8 -8 -22 -12 -8 +12
Timing Parameters
Subcarrier Programming
The color subcarrier is produced by an internal 28 bit Direct Digital Synthesizer (DDS) which is phase locked to the burst signal of the digitized video input. The nominal frequency is programmed into the DDS as follows: FREQ = (number of subcarrier cycles per line / number of pixels per line) * 2^28 An example would be NTSC subcarrier mode FREQ = (227.5 / 910) * 2^28 = 4000000 hex
BTV: The number of pixels between the start of the 16 pixel burst gate and the nominal start of active video. AV: The number of active pixels in the active video line. The difference between the sum of STB+BTV+AV subtracted from STS provides the nominal front porch.
Horizontal and Vertical Timing Parameters
When external horizontal and vertical syncs are provided the timing shown in Figure 28 is required to synchronize the internal state machines to beginning of a field (3, 5, or 7). For field 2 (4, 6, or 8) the falling edge of VSYNC must occur at least 2 clock periods but not more than (H-2) clock periods after the falling edge of HSYNC, where H is the total number of pixels in an active video line.
Horizontal Timing
The horizontal video line is broken down into four horizontal timing parameters.
STB
BTV
AV STS
65-22x5y-68
Figure 27. Horizontal Timing
REV. 1.0.0 2/4/03
61
TMC22x5yA
PRODUCT SPECIFICATION
CLOCK tHP tSP HSYNC
VSYNC
65-22x5y-12
Figure 28. External HSYNC and VSYNC Timing for Field 1 (3, 5, or 7)
Vertical Blanking
256 257 FIELDS 1 AND 3 258 259 260 0 1 2 3 4 5 6 *** 15 16 17 18
UVV HSYNC
UVV
EE
EE
EE
SS
SS
SS
EE
EE
EB
UBB
UBB
UBB
UVV
UVV
VSYNC FLD
258
259
FIELDS 2 AND 4 260 261 0 1 2 3 4 5 6 7 *** 16
17
18
19
UVV HSYNC
UVE
EE
EE
ES
SS
SS
SE
EE
EE
EB
UBB
UBB
UVV
UVV
UVV
VSYNC
FLD
65-22x5y-69
Figure 29. NTSC Vertical Interval
62
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
309
310
FIELDS 1 AND 5 ***
22
23
24
25
311
312
0
1
2
3
4
5
6
21
UVV HSYNC VSYNC FLD
-VE
EE
EE
SS
SS
SE
EE
EE
-BB
UBB
***
UBB
UVV
UVV
UVV
UVV
308
309
FIELDS 2 AND 6 310 311 0 1 2 3 4 5 6 7 *** 21 22
23
24
UVV
-VV
EE
EE
ES
SS
SS
EE
EE
EB
UBB
UBB
***
UBB
UBB
UVV
UVV
HSYNC VSYNC FLD
309
310
FIELDS 3 AND 7 ***
22
23
24
25
311
312
0
1
2
3
4
5
6
21
UVV HSYNC VSYNC FLD
-VE
EE
EE
SS
SS
SE
EE
EE
UBB
UBB
***
UBB
UVV
UVV
UVV
UVV
308
309
FIELDS 4 AND 8 310 311 0 1 2 3 4 5 6 7 *** 21 22
23
24
UVV HSYNC VSYNC FLD
UVV
EE
EE
ES
SS
SS
EE
EE
EB
-BB
UBB
***
UBB
UBB
UVV
UVV
65-22x5y-70
Figure 30. PAL-B,G,H,I,N Vertical Interval
REV. 1.0.0 2/4/03
63
TMC22x5yA
PRODUCT SPECIFICATION
258
259 260 261 262
FIELDS 1 AND 5 0 1 2 3 4 5 6 7 8 *** 16
17
UVV HSYNC VSYNC FLD
UVV
EE
EE
EE
SS
SS
SS
EE
EE
EE
-BB
-BB
UBB
***
UBB
UVV
258
259 260 261
FIELDS 2 AND 6 0 1 2 3 4 5 6 7 8 *** 16
17
18
UVV HSYNC VSYNC FLD
-VE
EE
EE
ES
SS
SS
SE
EE
EE
EB
-BB
UBB
***
UBB
UVV
UVV
258
259 260 261 262
FIELDS 3 AND 7 0 1 2 3 4 5 6 7 8 *** 16
17
UVV HSYNC VSYNC FLD
-VV
EE
EE
EE
SS
SS
SS
EE
EE
EE
-BB
UBB
UBB
***
UBB
UVV
257
258
259 260 261
FIELDS 3 AND 7 0 1 2 3 4 5 6 7 8 *** 16
17
18
UVV HSYNC VSYNC FLD
-VV
-VE
EE
EE
ES
SS
SS
SE
EE
EE
EB
UBB
UBB
***
UBB
UVV
UVV
65-22x5y-71
Figure 31. PAL-M Vertical Interval
64
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
VINDO Operation
The VINDO circuit uses the line idents on LID4-0, and the blanking signals to control the comb filter output and the blanking of the YUV data in the output matrix during the vertical blanking period. The vertical window VINDO starts on the first line after the last equalizing pulse, at LID4-0 = 02. The VINDO stays HIGH from this line until the VINDO count = VINDO4-0, or the VBLK signal goes HIGH, at which time the VINDO goes LOW. While the VINDO is HIGH the decoder operation is controlled by VDIV, and during the time the VINDO and VBLK are LOW the decoder operation is controlled by VDOV.
Video Measurement
The TMC22x5yA supports a comprehensive set of video measurement techniques to aid the user in setting up the gain, phase, etc. of the decoder and in tracking down system errors.
Pixel Grab
The pixel grab allows the user to grab one pixel every line, or one pixel out of the four field sequence in NTSC or the 8 field sequence in PAL, under software control. The SET pin can also be used to produce the pixel grab pulse if SET2-0 = 110 and PGEXT is set HIGH. The 10 bit G/Y, B/U, R/V outputs are stored in one set of four 8 bit registers in the FORMAT block, while the 10 bit luma and mixed sync data and the 10 bit demodulated U and V color difference signals are stored in a set of five 8 bit registers in the GRAB circuit block. The pixel grab signal, PIXEL, whether internally or externally generated, is internally delayed to ensure that the all the grabbed data are from the same pixel relative to the line sync pulse. The PIXEL signal is equal to PGRAB or the logical AND of PGRAB with FGRAB and LGRAB, and is controlled by the LPGEN, PGEN, and PGEXT register bits. The luma and mixed sync signals are multiplexed on the YMS data bus and the U and V signals are multiplexed on the UV data bus, at the PXCK clock rate. The pixel grab signal accommodates for this when grabbing these components. An example of the pixel grab feature, is grabbing a pixel in the center of the burst period allowing the user to check the burst height by reading the magnitude of the demodulated U and V components. This allows the user to compensate for any chrominance gain errors in the output matrix.
Table 22. PAL VINDO operation
LID4-0 00 - 01 02 - 0A 02 - 0A 02 - 0A 02 - 0A 0B - 17 VINDO x 1 1 0 0 x VDIV x 0 1 x x x VDOV x x x 0 1 x Y normal simple flat black simple normal C normal simple black black black normal
NTSC VINDO operation
LID4-0 00 - 02 03 - 06 03 - 06 03 - 06 03 - 06 07 - 17 VINDO x 1 1 0 0 x VDIV x 0 1 x x x VDOV x x x 0 1 x Y normal simple flat black simple normal C normal simple black black black normal
Y Video A Video B Luma and Chroma Separation Y Data dT Luma Proc
YMS MS U UV G/Y Output Matrix Output Formatter and Buffer B/U R/V
C Data Chroma Demodulation
LPF
LPF
V
U Data Grab register 3A/3C V Data Grab register 3B/3C Y Data Grab register 38/3C MS Data Grab register 39/3C G/Y Grab register 34/37 B/U Grab register 35/37 RV Grab register 36/37
Pixel
dT
65-22x5y-72
Figure 32. Pixel Grab Locations
REV. 1.0.0 2/4/03
65
TMC22x5yA
PRODUCT SPECIFICATION
Table 23. Pixel Grab Control
LGEXT PGEN PGEXT LGEN 0 0 0 0 1 1 x 0 0 x 0 1 GRABS signal GRABS = 0 GRABS = PGRAB GRABS = FGRAB & LGRAB & PGRAB GRABS = NOT (SET pin) GRABS = PGRAB GRABS = NOT (SET pin)
The SET pin can be used to provide an external grab signal when PGEXT is set HIGH in register 30h and the SET function in register 00h, SET[2:0] is programmed to 110 (binary). In this mode the falling edge on the SET pin triggers the pixel grab. The GRABP, GRABL, and GRABF signals are available on bits 0,1, and 2 respectively of the read only register 41. An example of the pixel grab feature, would be grabbing a pixel in the center of the burst period allowing the user to check the burst height by reading the magnitude of the demodulated U and V components. This would then allow the user to compensate for any chrominance gain errors in the output matrix. The pixel grab value is delayed by 29 pixels from the pixel count. This is the delay for all the pixel grab registers. Figure 33 shows this delay relative to GHSYNC. This means that if 29 is placed in the PG value, the actual pixel grabbed is pixel 0. The top two bits of the PG value provide the quadrant and the bottom 9 bits provide the offset within that quadrant. The integer part of STS/4 gives the maximum count for each quadrant while the fractional result (bottom two bits) provides the 0,1,2, or 3 count offset for the last quadrant. For pixels value <= 4*Int(STS/4) PG[10:9] = quadrant number PG[8:0] = max quadrant count - Int(STS/4) + pixel offset For pixels value > 4*Int(STS/4) The quadrant is always number 3, ie PG[10:9] = 11 while the pixel in excess of 4*Int(STS/4) is added to 1536.
0 1 1
1 x x
1 0 1
x x x
If a single pixel every 4 fields in NTSC and 8 fields in PAL is required to be grabbed, PGG and PGEN in register 30h should be set HIGH. The pixel grab signal is the logical AND of the GRABP, GRABL, and GRABF signals. GRABP goes HIGH whenever the pixel count equals the programmed pixel grab number, GRABL goes HIGH for one line whenever the line count equals the programmed line number, and the GRABF goes HIGH for a field whenever the field number equals the programmed field count. If the same pixel on every line is required to be grabbed, then PGG should be set LOW, which internally forces GRABL and GRABF to be forced HIGH enabling the pixel grab whenever GRABP goes HIGH.
Pixel STS-1 STS-1
Pixel Count
0 Pixel 0 GHSYNC 1 0
STS-1
Pixel Grab
0 Pixel Grab value 0 Pixel Grab value 28
29 pixels
Figure 33. Relationship Between Pixel Count and Pixel Grab Value
66
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Examples: NTSC std with STS programmed to 858. Base pixels per quadrant = Int(858/4) = 214 Pixel 0: 1. Pixel 0 <= 4*Int(858/4) 2. Required pixel 0 < 214 therefore quadrant = 0, [PG[10:9] = 00] 3. PG[10:0] = 511 - 214 + (0+[0*214]) = 297 Pixel 56: 1. Pixel 56 <= 4*Int(858/4) 2. Required pixel 56 < 214 therefore quadrant = 0 [PG[10:9] = 00] 3. PG[10:0] = 511 - 214 + (56-[0*214]) = 353 Pixel 250: 1. Pixel 250 <= 4*Int(858/4) 2. Required pixel 250 > 214 therefore quadrant =/= 0 3. Required pixel 250 < 428 therefore quadrant = 1, [PG[10:9] = 01] 4. PG[10:0] = 1023 - 214 + (250-[1*214]) = 845 Pixel 800: 1. Pixel 800 <= 4*Int(858/4) 2. Required pixel 800 > 214 therefore quadrant =/= 0 3. Required pixel 800 > 428 therefore quadrant =/= 1 4. Required pixel 800 > 642 therefore quadrant =/= 2 5. Required pixel 800 < 858 therefore quadrant = 3, [PG[10:9] = 11] 6. PG[10:0]= 2047 - 214 + (800-[3*214]) = 1991 Pixel 856: 1. Pixel <= 4*Int(858/4) 2. Required pixel 856 > 214 therefore quadrant =/= 0 3. Required pixel 856 > 428 therefore quadrant =/= 1 4. Required pixel 856 > 642 therefore quadrant =/= 2 5. Required pixel 856 < 858 therefore quadrant = 3, [PG[10:9] = 11] 6. PG[10:>0] = 2047 - 214 + (856-[3*214]) = 2047 Pixel 857: 1. Pixel 857 > 4*Int(858/4) 2. Therefore quadrant = 3, [PG[10:9] = 11] 3. PG[10:0] = 1536 + (857-[4*214]) = 1537
cycle for the frozen line store is still clocked by PCK. The subcarrier DDS and the internal read only registers will be updated once per clock period as normal, but will reload the DRS SEED and PHASE values at the beginning of each line. The G/Y, B/U, and R/V outputs will remain active, and the DHSYNC and DVSYNC signals will remained locked to the input or flywheel if the input has been removed. The pixel grab function can be used in conjunction with the frozen line to examine individual pixels inside the decoder.
Parallel Microprocessor Interface
The parallel microprocessor interface, active when SER is HIGH, employs a 12-line interface, with an 8-bit data bus and one address bit: two addresses are required for device programming and pointer-register management. Address bit 0 selects between reading/writing the register addresses and reading/writing register data. When writing, the address is presented along with a LOW on the R/W pin during the falling edge of CS Eight bits of data are presented on D7-0 during the subsequent rising edge of CS. One additional falling edge of CS is needed to move input data to its assigned working registers. In read mode, the address is accompanied by a HIGH on the R/W pin during a falling edge of CS. The data output pins go to a low-impedance state tDOZ after CS falls. Valid data are present on D7-0 tDOM after the falling edge of CS. Because this port operates asynchronously with the pixel timing, there is an uncertainty in this data valid output delay of one PXCK period. This uncertainty does not apply to tDOZ. Writing data to specific control registers of the TMC22x5yA requires that the 8-bit address of the control register of interest be written. This control register address is the base address for subsequent write operations. The base address autoincrements by one for each byte of data written after the data byte intended for the base address. If more bytes are transferred than there are available addresses, the address will not increment and remain at its maximum value of 3Fh.
Table 24. Parallel Port Control
A1-0 R/W 00 00 01 01 10 10 11 11 0 1 0 1 0 1 0 1 Action Load D7-0 into Control Register pointer (block 00) Read Control Register pointer on D7-0 Load D7-0 into addressed XLUT Location pointer (block 01) Read addressed XLUT Location pointer on D7-0. Write D7-0 to addressed Control Register Read addressed Control Register on D7-0 Write D7-0 to addressed XLUT Location Read addressed XLUT Location on D7-0
Composite Line Grab
The composite line grab is only available in the 3 line comb based decoders (TMC22053A and TMC22153A), and allows the user to grab any line from the 4 field sequence in NTSC or 8 field sequence in PAL when LGEN is set HIGH. When the LGEN register bit is set HIGH the decoder automatically switches to operate as a "simple" bandsplit decoder. The SET pin can also be used to produce the line grab pulse if SET2-0 = 110 and LGEXT is set HIGH. Once the line grab has been activated the subcarrier oscillator is frozen with the SEED and phase from the beginning of the line, and the composite video in the 1H line store is frozen by disabling the write signals in LSTORE1. The read
REV. 1.0.0 2/4/03
67
TMC22x5yA
PRODUCT SPECIFICATION
tPWLCS CS tSA R/W tHA
tPWHCS
ADR tSD D7-0
65-22x5y-16
tHD
Figure 33. Microprocessor Parallel Port - Write Timing
tPWLCS CS tSA R/W tHA tPWHCS
ADR tDOM D7-0 tDOZ
65-22x5y-17
tHOM
Figure 34. Microprocessor Parallel Port - Read Timing
Serial Control Port (R-Bus)
In addition to the 12-wire parallel port, a 2-wire serial control interface is provided, and active when SER is LOW. Either port alone can control the entire chip. Up to eight TMC22x5yA devices may be connected to the 2-wire serial interface with each device having a unique address. The 2-wire interface comprises a clock (SCL) and a bi-directional data (SDA) pin. The Decoder acts as a slave for receiving and transmitting data over the serial interface. When the serial interface is not active, the logic levels on SCL and SDA are pulled HIGH by external pull-up resistors. Data received or transmitted on the SDA line must be stable for the duration of the positive-going SCL pulse. Data on SDA must change only when SCL is LOW. If SDA changes state while SCL is HIGH, the serial interface interprets that action as a start or stop sequence.
There are six components to serial bus operation: * * * * * * Start signal Slave address byte Block Pointer Base register address byte Data byte to read or write Stop signal
When the serial interface is inactive (SCL and SDA are HIGH) communications are initiated by sending a start signal. The start signal is a HIGH-to-LOW transition on SDA while SCL is HIGH. This signal alerts all slaved devices that a data transfer sequence is coming. The first eight bits of data transferred after a start signal comprise a seven bit slave address (the first seven bits) and a single R/W bit (the eighth bit). The R/W bit indicates the direction of data transfer, read from or write to the slave device. If the transmitted slave address matches the address of the device (set by the state of the SA2-0 input pins in Table 20), the TMC22x5yA acknowledges by bringing SDA LOW on the 9th SCL pulse. If the addresses do not match, the TMC22x5yA does not acknowledge.
68
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Table 25. Serial Port Addresses
bit 7 A6 (MSB) 1 1 1 1 1 1 1 1 bit 6 A5 0 0 0 0 0 0 0 0 bit 5 A4 1 1 1 1 1 1 1 1 bit 4 A3 1 1 1 1 1 1 1 1 bit 3 bit 2 bit 1 A2 A1 A0 (SA2) (SA1) (SA0) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
Reading (the R/W bit of the slave address byte HIGH) begins at the previously established base address. The address of the read register autoincrements after each byte is transferred. To terminate a write sequence to the TMC22x5yA, a stop signal must be sent. A stop signal comprises a LOW-toHIGH transition of SDA while SCL is HIGH. To terminate a read sequence simply do not acknowledge (NOACK) the last byte received and the TMC22x5yA will terminate the sequence. A repeated start signal occurs when the master device driving the serial interface generates a start signal without first generating a stop signal to terminate the current communication. This is used to change the mode of communication (read, write) between the slave and master without releasing the serial interface lines.
Serial Interface Read/Write Examples
Data Transfer via Serial Interface
For each byte of data read or written, the MSB is the first bit; that is, bit 7 of the 8-bit sequence. If the TMC22x5yA does not acknowledge the master device during a write sequence, the SDA remains HIGH so the master can generate a stop signal. If the master device does not acknowledge the TMC22x5yA during a read sequence, the Decoder interprets this as "end of data." The SDA remains HIGH so the master can generate a stop signal. Writing data to specific control registers of the TMC22x5yA requires that the 8-bit address of the control register of interest be written after the slave address has been established. This control register address is the base address for subsequent write operations. The base address autoincrements by one for each byte of data written after the data byte intended for the base address. If more bytes are transferred than there are available addresses, the address will not increment and remain at its maximum value of 3Fh. Any base address higher than 3Fh will not produce an ACKnowledge signal. Data are read from the control registers of the TMC22x5yA in a similar manner. Reading requires two data transfer operations: The base address must be written with the R/W\ bit of the slave address byte LOW to set up a sequential read operation.
Write to one control register * * * * * * Start signal Slave Address byte (R/W bit = LOW) Block Pointer (00) Base Address byte Data byte to base address Stop signal
Write to four consecutive XLUT locations * * * * * * * * * Start signal Slave Address byte (R/W bit = LOW) Block Pointer (01) Base Address byte Data byte to base address Data byte to (base address + 1) Data byte to (base address + 2) Data byte to (base address + 3) Stop signal
Read from one XLUT location * Start signal * Slave Address byte (R/W bit = LOW)
SDA tBUFF tSTAH SCL tBAH
65-22x5y-18
tDHO tDAL
tDSU
tSTASU
tSTOSU
Figure 35. Serial Port Read/Write Timing
REV. 1.0.0 2/4/03
69
TMC22x5yA
PRODUCT SPECIFICATION
* * * * * * *
Block Pointer (01) Base Address byte Stop signal Start signal Slave Address byte (R/W bit = HIGH) Data byte from base address Stop signal
Read from four consecutive control registers * Start signal * Slave Address byte (R/W bit = LOW) * Block Pointer (00)
* * * * * * * * *
Base Address byte Stop signal Start signal Slave Address byte (R/W bit = HIGH) Data byte from base address Data byte from (base address + 1) Data byte from (base address + 2) Data byte from (base address + 3) Stop signal
(MSB) SDA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
(LSB) Bit 0 ACK
SCL
65-22x5y-19
Figure 36. Serial Interface - Typical Byte Transfer
SDA
A6
A5
A4
A3
A2
SA2
SA1
SA0
ACK
SCL
65-22x5y-19A
Figure 37. Serial Interface - Chip Address *Note: To read from the XLUT, the initial read must be a dummy read. This means, for example, to read back XLUT location 0x02, read back location 0x01, then read back 0x02 and ignore the information read back from the 0x01 location. This only needs to be done once in a sequence. To read back the entire XLUT, set the pointer to 0xFF and ignore the data read from this register. The pointer will then auto-increment to 0x00 allowing the next 256 locations read to be valid.
70
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Equivalent Circuits and Threshold Levels
VDD VDD
p Digital Input n
p Digital Output n
27011B 27014B
GND
GND
Figure 38. Equivalent Digital Input Circuit
Figure 39. Equivalent Digital Output
tDIS SET or RESET 0.5V Three-State Outputs 0.5V 2.0V 0.8V
65-22x5y-76
tENA
Figure 40. Threshold Levels for Three-state
REV. 1.0.0 2/4/03
71
TMC22x5yA
PRODUCT SPECIFICATION
Absolute Maximum Ratings (beyond which the device may be damaged)1
Parameter Power Supply voltage Digital Inputs Applied Voltage Forced current Digital Outputs Applied voltage 2 Forced current 3, 4 Short circuit duration (single output in HIGH state to ground) Analog Output Short circuit duration (all outputs to ground) Temperature Operating, ambient junction Lead, soldering (10 seconds) Vapor Phase soldering (1 minute) Storage -20 110 140 300 220 150 C C C C C -0.5 -3.0 VDD+0.5 +6.0 1 second infinite V mA
3, 4
Min. -0.5 -0.5 -20.0
Max. +7.0 VDD+0.5 +20.0
Unit V V mA
Notes: 1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded. 2. Applied voltage must be current limited to specified range. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current flowing into the device.
tPWHCK PXCK tSP2 HSYNC tHP2
tPWLCK
CVBS
PIXEL 0 tSPI tHPI
PIXEL 1
PIXEL 2
Internal PCK tCLH LDV
65-22x5y-77
Figure 41. Input Timing Parameters
72
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Operating Conditions
Parameter VDD VIH Power Supply Voltage Input Voltage, Logic HIGH TTL Compatible Inputs Serial Port (SDA and SCL) VIL Input Voltage, Logic LOW TTL Compatible Inputs Serial Port (SDA and SCL) IOH IOL TA fCLK tPWHCK tPWLCK tSP tHP tSP tHP Output Current, Logic HIGH Output Current, Logic LOW Ambient Temperature, Still Air Pixel Rate (CKSEL = 0) Master Clock Rate = 2X pixel rate (CKSEL = CLOCK pulse width, HIGH CLOCK pulse width, LOW Pixel Data Input Setup Time Pixel Data Input Hold Time HSYNC, VSYNC, and BUFFER setup time HSYNC, VSYNC, and BUFFER hold time 1)1 0 10 20 8 13 8 2 5 6 GND GND 0.8 0.3*VDD -2.0 4.0 70 18 36 V V mA mA C MHz MHz ns ns ns ns ns ns 2.0 0.7*VDD VDD V V Min. 4.75 Nom. 5.0 Max. 5.25 Units V
Pixel Interface (input)
Notes: 1. Tested at fCLK = 30MHz
To aid in the understanding of the timing relationship between the PXCK and LDV clock, when the LDV signal is used as the TMC22x5yA output clock, the following block diagram of the TMC22x5yA output stage is provided.
Data In
D
Q
D
Q
G/Y, B/U, and R/V Output Data
PXCK
Ck
Ck
2:1 mux LDV
65-22x5y-78
Figure 42. Functional Block Diagram of the TMC22x5yA G/Y, B/U, and R/V Output Stage
REV. 1.0.0 2/4/03
73
TMC22x5yA
PRODUCT SPECIFICATION
Operating Conditions (continued)
Parameter Pixel Interface (output) Min. 4 4 4 2.5 2.5 2.5 23 23 9 10 30 30 0 14 Nom. 15 15 15 Max. 18 18 18 Units ns ns ns ns ns ns ns ns ns ns
tPOD CLOCK to DHSYNC and DVYSNC, AVOUT, and FID[2:0] Propagation
Time
tPOD CLOCK to data, Propagation Time tPOD Int. or Ext. LDV to data, Propagation Time
tHOD Clock to DHSYNC and DVSYNC, AVOUT, and FID[2:0] Hold Time tHOD Clock to Data, Hold Time tHOD Int. or Ext. LDV to Data, Hold Time tENA tDIS Enable to Low Z on Output Data Disable to High Z on Output Data CLOCK to LDV (i/p) signal HIGH CLOCK to LDV (o/p) signal HIGH
tCLH tCLH
PXCK
tPOD
tPOD
DHSYNC
G/Y, B/U RV Data TMC22x5y Internal PCK
PIXEL 0
PIXEL 1
PIXEL 2
tCLH LDV
65-22x5y-79
Figure 43. Output Timing Parameters
74
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Operating Conditions (continued)
Parameter Parallel Microprocessor Interface tPWLCS tPWHCS tSA tHA tSD tHD tDAL tDAH tSTAH tSTASU tSTOSU tBUFF tDSU CS Pulse Width, LOW CS Pulse Width, HIGH Address Setup Time Address Hold Time Data Setup Time (write) Data Hold Time (write) SCL Pulse Width , LOW SCL Pulse Width, HIGH Hold Time for START or Repeated START Setup Time for START or Repeated START Setup time for STOP Bus Free Time Betweeen a STOP and a START condition Data Setup Time 2 3 8 2 8 2 1.0 0.48 0.48 0.48 0.48 1.0 80 Pixels Pixels ns ns ns ns s s s s s s ns Min. Nom. Max. Units
Serial Microprocessor Interface
Electrical Characteristics
Parameter IDD IIH IIL IOZH IOZL IOS VOH VOL Power Supply Current1 IDDQ Power Supply Current, Disabled Input Current, HIGH Input Current, LOW Hi-Z Output Leakage Current, Output HIGH Hi-Z Output Leakage Current, Output LOW Short-Circuit Current Output Voltage, HIGH Output Voltage, LOW G/Y9-0, etc2., IOH = MAX G/Y9-0, etc2., IOL = MAX SDA, IOL = 3mA SDA, IOL = 6mA CI CO Digital Input Capacitance Digital Output Capacitance 4 10 Conditions VDD = Max, fPXCK = 27MHz VDD = Max VDD = Max, VIN = VDD VDD = Max, VIN = 0V VDD = Max, VIN = VDD VDD = Max, VIN = 0V -20 2.4 0.4 0.4 0.6 10 Min. Typ. 225 Max. 275 50 10 10 10 10 -80 Units mA mA A A A A mA V V V V pF pF
Notes: 1. Typical IDD with VDD = NOM and TA = NOM, Maximum IDD with VDD = 5.25V and TA = 70C 2. G/Y[9:0], B/Y[9:0], R/V[9:0] , DVSYNC, DHSYNC, LDV, AVOUT, FID[2:0]
REV. 1.0.0 2/4/03
75
TMC22x5yA
PRODUCT SPECIFICATION
Switching Characteristics
Parameter tDOZ tHOM tDOM Output Delay, CS to low-Z Output Hold Time, CS to high-Z Output Delay, CS to Data Valid Conditions Min. 9 10 30 40 Typ. Max. Units ns ns ns
Note: Timing reference points are at the 50% level, digital output load <40pF.
System Performance Characteristics
Parameter RES Video Processing Resolution Conditions TMC2205xA TMC2215xA Min. Typ. 8 10 Max. Units bits bits
76
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Programming Examples
Standard: Mode: Input Format: Output Format: Decoder: Register Map: 0 0 1 2 3 D8 5A 40 00 1 01 56 F8 00 2 00 2E E0 00 3 A1 D2 43 00 4 20 23 00 00 5 28 00 00 00 6 00 00 07 00 7 10 2C 00 00 8 40 1B 00 00 9 00 90 00 00 A 12 13 00 00 B 00 49 00 00 C 00 F0 00 00 D 04 01 00 00 E 24 00 00 00 F 09 00 00 00 NTSC-M Line-Locked 13.5 Composite RGB (0-1023) Sync on Green Adaptive 3-Line Chroma Comb Filter
Standard: Mode: Input Format: Output Format: Decoder: Register Map: 0 0 1 2 3 C0 5A 40 00 1 01 56 F8 00
NTSC Line-Locked NTSC Composite D1 Component 3 Line Adaptive Chroma Comb
2 00 2E E0 00
3 A1 D2 43 00
4 20 23 24 00
5 28 72 25 00
6 00 00 07 00
7 10 00 00 00
8 40 95 00 00
9 00 0E 00 00
A 34 51 00 00
B 74 49 00 00
C 80 40 00 00
D 04 00 00 00
E 64 00 00 00
F 08 00 00 00
REV. 1.0.0 2/4/03
77
TMC22x5yA
PRODUCT SPECIFICATION
Programming Examples (continued)
Standard: Mode: Input Format: Output Format: Decoder: Register Map: 0 0 1 2 3 D8 5A 40 00 1 01 56 F8 00 2 00 2E E0 00 3 A1 D2 43 00 4 20 23 24 00 5 28 3C 25 00 6 00 00 07 00 7 10 2C 00 00 8 40 1B 00 00 9 00 90 00 00 A 34 13 00 00 B 00 49 00 00 C 80 F0 00 00 D 04 01 00 00 E 64 00 00 00 F 08 00 00 00 NTSC Line-Locked 13.5 MHz Composite Video YUV Adaptive 3-Line Comb
Standard: Mode: Input Format: Output Format: Decoder: Register Map: 0 0 1 2 3 DB 60 90 00 1 01 53 15 00
PAL Line-Locked Composite YUV Adaptive 3-Line Comb
2 00 32 13 00
3 24 CE 54 00
4 08 23 24 00
5 00 01 25 00
6 24 00 07 00
7 15 00 00 00
8 40 00 00 00
9 08 3E 00 00
A 36 03 00 00
B 00 49 00 00
C C0 00 00 00
D 04 05 00 00
E 54 00 00 00
F 09 00 00 00
78
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Programming Examples (continued)
Standard: Mode: Input Format: Output Format: Decoder: Register Map: 0 0 1 2 3 D3 60 90 00 1 07 53 15 00 No Comb 2 00 44 13 00 3 00 D2 54 00 4 20 23 00 00 5 00 00 00 00 6 00 00 00 00 7 0C 00 00 00 8 40 88 00 00 9 08 BF 00 00 A 24 3C 00 00 B 60 49 00 00 C 03 40 00 00 D 00 00 00 00 E 0B 00 00 00 F 0A 00 00 00 PAL Line-Locked PAL-YC Y, Cb, Cr (D1 Out)
Standard: Mode: Input Format: Output Format: Decoder: Register Map: 0 0 1 2 3 C0 5A 00 00 1 1F 47 00 00
NTSC-M D1 Mode D1, CBYCR [Y] multiplexed data w/embedded TRS words D1 Output 2 Line Chroma comb of CBCR data
2 37 35 00 00
3 E3 D2 00 00
4 20 23 00 00
5 00 00 00 00
6 00 0A 00 00
7 0C 00 00 00
8 40 00 00 00
9 40 00 00 00
A 34 00 00 00
B 60 49 00 00
C 09 40 00 00
D 04 00 00 00
E F8 00 00 00
F 02 00 00 00
REV. 1.0.0 2/4/03
79
TMC22x5yA
PRODUCT SPECIFICATION
Programming Examples (continued)
Standard: Mode: Input Format: Output Format: Decoder: Register Map: 0 0 1 2 3 C0 5A 00 00 1 1F 47 00 00 2 37 35 00 00 3 E3 D2 00 00 4 20 23 00 00 5 00 00 00 00 6 00 0A 00 00 7 0C 00 00 00 8 40 00 00 00 9 40 00 00 00 A 34 00 00 00 B 00 49 00 00 C 09 40 00 00 D 04 00 00 00 E 0A 00 00 00 F 02 00 00 00 NTSC-M D1 Mode D1, CBYCR [Y] Multiplexed Data w/TRS YCBCR, Output DHSync + DVSync Simple Transcoder
Standard: Mode: Input Format: Output Format: Decoder: Register Map: 0 0 1 2 3 C0 5A 00 00 1 0F 47 00 00
NTSC-M D1 Mode YCBCR D1, CBYCR [Y] Multiplexed Data with TRS Simple Transcoder
2 07 35 00 00
3 A3 D2 00 00
4 20 23 00 00
5 00 00 00 00
6 00 00 00 00
7 0C 00 00 00
8 40 00 00 00
9 00 00 00 00
A 34 00 00 00
B 60 49 00 00
C 09 40 00 00
D 04 00 00 00
E 0A 00 00 00
F 02 00 00 00
80
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Programming Worksheet
Standard: Mode: Input Format: Output Format: Decoder: Register Map: 0 0 1 2 The DRS appears on the
Bandsplit Filter
0 -10 Attenuation (dB) Bandsplit Filter 2 Attenuation (dB) -20 -30 -40 -50 -60 0.00 0.10 0.20 0.30 0.40 -70 Bandsplit Filter 1
65-22x5y-40
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
xx output at the rate.
xx
xx
xx
xx
xx
xx
xx
xx
Demodulation Filter
0 -10 -20 -30 -40 -50 -60 -70 0.00 0.10 0.20 0.30 0.40 Demodulator Filter 2
65-22x5y-41
Demodulator Filter 1
0.50
Normalized Frequency
Normalized Frequency
Adaptive Notch Filter
0 -10 Attenuation (dB) Attenuation (dB) -20 -30 -40
65-22x5y-42
Non-Adaptive Notch Filter
0 -10 -20 -30 -40
65-22x5y-43
Adaptive Notch Filter 3
Adaptive Notch Filter 1
-50 -60 -70 0.00 0.10 0.20 0.30 0.40 Adaptive Notch Filter 2
-50 -60 -70 0.00 0.10 0.20 0.30 0.40
0.50
Normalized Frequency
Normalized Frequency
REV. 1.0.0 2/4/03
0.50
0.50
81
TMC22x5yA
PRODUCT SPECIFICATION
Notes
82
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Mechanical Dimensions - 100 Lead MQFP Package
Symbol A A1 A2 B C D D1 E E1 e L N ND NE
ccc
Inches Min. -- .010 .100 .009 .005 .904 .783 .667 Max. .134 -- .120 .015 .009 .923 .791 .687
Millimeters Min. -- .25 2.55 .23 .13 22.95 19.90 16.95 Max. 3.40 -- 3.05 .38 .23 23.45 20.10 17.45
Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982. 2. Controlling dimension is millimeters. 3. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be .08mm (.003in.) maximum in excess of the "B" dimension. Dambar cannot be located on the lower radius or the foot. 4. "L" is the length of terminal for soldering to a substrate. 5. "B" & "C" includes lead finish thickness.
3, 5 5
.547 .555 .0256 BSC .025 .037 100 30 20 0 -- 7 .004
13.90 14.10 .65 BSC .65 .95 100 30 20 0 -- 7 .10
4
D D1 Datum Plane B E1 .13 (.005) R Min. E e 0.063" Ref (1.60mm) Lead Detail L .20 (.008) Min. 0 Min. .13 (.30) R .005 (.012) C
See Lead Detail A A2 B A1 Seating Plane Base Plane -CLead Coplanarity ccc C
REV. 1.0.0 2/4/03
83
TMC22x5yA
PRODUCT SPECIFICATION
Ordering Information
Product Number TMC22051AKHC TMC22052AKHC TMC22053AKHC TMC22151AKHC TMC22152AKHC TMC22153AKHC Temperature Range 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C Decoding Simple 2-Line Comb 3-Line Comb Simple 2-Line Comb 3-Line Comb Resolution 8 bit 8 bit 8 bit 10 bit 10 bit 10 bit Package 100-Lead MQFP 100-Lead MQFP 100-Lead MQFP 100-Lead MQFP 100-Lead MQFP 100-Lead MQFP Package Marking 22051AKHC 22052AKHC 22053AKHC 22151AKHC 22152AKHC 22153AKHC
2/4/03 0.0m 001 Stock#DS7022x5yA

▲Up To Search▲

Price & Availability of TMC22053AKHC

	To Download TMC22053AKHC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .